]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: expose the VA above the hole to userspace
authorChristian König <christian.koenig@amd.com>
Tue, 7 Nov 2017 11:03:31 +0000 (12:03 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Dec 2017 17:48:05 +0000 (12:48 -0500)
Let userspace know how much area we have above the 48bit VA hole on
Vega10.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
include/uapi/drm/amdgpu_drm.h

index 2614269c4d7fda3a77e2a546f00d34d0c4c8ccc8..3222e1d4636c4fcb2bac5753b4405d2986b0c75f 100644 (file)
@@ -550,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
        }
        case AMDGPU_INFO_DEV_INFO: {
                struct drm_amdgpu_info_device dev_info = {};
+               uint64_t vm_size;
 
                dev_info.device_id = dev->pdev->device;
                dev_info.chip_rev = adev->rev_id;
@@ -577,10 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                        dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
                if (amdgpu_sriov_vf(adev))
                        dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
+
+               vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
                dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
                dev_info.virtual_address_max =
-                       min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
-                           AMDGPU_VA_HOLE_START);
+                       min(vm_size, AMDGPU_VA_HOLE_START);
+
+               vm_size -= AMDGPU_VA_RESERVED_SIZE;
+               if (vm_size > AMDGPU_VA_HOLE_START) {
+                       dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
+                       dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
+               }
                dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
                dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
                dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
index 0e23ce3f31137146217e79f89d25093716bd386d..4d21191aaed0f92aeb5cfd3e345b9befa8e549f8 100644 (file)
@@ -877,6 +877,10 @@ struct drm_amdgpu_info_device {
        __u32 _pad1;
        /* always on cu bitmap */
        __u32 cu_ao_bitmap[4][4];
+       /** Starting high virtual address for UMDs. */
+       __u64 high_va_offset;
+       /** The maximum high virtual address */
+       __u64 high_va_max;
 };
 
 struct drm_amdgpu_info_hw_ip {