ARM: tegra: Add SOR0_OUT clock on Tegra124

This clock is needed for eDP to properly function, so add it to the SOR
device tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b113e47b2b2a2247df4f3e5d032e1fa1087028e3..413bfb981de8ca992bffdfc557d0ec72745478c3 100644 (file)
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -157,10 +157,11 @@ sor@54540000 {
                        reg = <0x0 0x54540000 0x0 0x00040000>;
                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA124_CLK_SOR0>,
+                                <&tegra_car TEGRA124_CLK_SOR0_OUT>,
                                 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
                                 <&tegra_car TEGRA124_CLK_PLL_DP>,
                                 <&tegra_car TEGRA124_CLK_CLK_M>;
-                       clock-names = "sor", "parent", "dp", "safe";
+                       clock-names = "sor", "out", "parent", "dp", "safe";
                        resets = <&tegra_car 182>;
                        reset-names = "sor";
                        status = "disabled";