drm/i915/cnl: use previous pll hw readout

By the time cnl_ddi_clock_get() is called we've just got the hw state
from the pll registers. We don't need to read them again: we can rather
reuse what was cached in the dpll_hw_state.

This also affects the code for ICL since it partially reuses the CNL
code. However the more intricate part on ICL is left for another patch.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190322223751.22089-4-lucas.demarchi@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 92440ff48f93287d70df8ad4d66faacb576b8475..1395338c6772cead5601e1aa15bf05c07ef2ce31 100644 (file)
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1179,11 +1179,10 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-       u32 pll_id;
 
        /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
-       pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
-       pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+       pipe_config->port_clock =
+               cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
        pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
        pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 975dbf6c7fba21064eaf8c7415141ca5a4c1881b..0e8f20d9ab2a2043adb8175dc88399316be1724b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1296,24 +1296,15 @@ static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
 }
 
 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
-                       enum intel_dpll_id pll_id)
+                       struct intel_dpll_hw_state *pll_state)
 {
-       u32 cfgcr0, cfgcr1;
        u32 p0, p1, p2, dco_freq, ref_clock;
 
-       if (INTEL_GEN(dev_priv) >= 11) {
-               cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
-               cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
-       } else {
-               cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
-               cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
-       }
-
-       p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
-       p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
+       p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+       p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
 
-       if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
-               p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
+       if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
+               p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
                        DPLL_CFGCR1_QDIV_RATIO_SHIFT;
        else
                p1 = 1;
@@ -1348,9 +1339,10 @@ int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 
        ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
 
-       dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
+       dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
+               * ref_clock;
 
-       dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+       dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
                      DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
 
        if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
@@ -1463,13 +1455,14 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
                              struct intel_crtc_state *pipe_config)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
        enum port port = encoder->port;
-       int link_clock = 0;
+       int link_clock;
        u32 pll_id;
 
        pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
        if (intel_port_is_combophy(dev_priv, port)) {
-               link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+               link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
        } else {
                if (pll_id == DPLL_ID_ICL_TBTPLL)
                        link_clock = icl_calc_tbt_pll_link(dev_priv, port);
@@ -1485,18 +1478,13 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder,
                              struct intel_crtc_state *pipe_config)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       int link_clock = 0;
-       u32 cfgcr0;
-       enum intel_dpll_id pll_id;
-
-       pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
-
-       cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+       struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
+       int link_clock;
 
-       if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
-               link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
+       if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
+               link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
        } else {
-               link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
+               link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
 
                switch (link_clock) {
                case DPLL_CFGCR0_LINK_RATE_810:

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 97fcbbd65e64495682f716d9a79d23eb638621e8..6102d21a8ba812a4748675d9b4fa8f9b2b56c4a9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1659,7 +1659,7 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
                                     bool enable);
 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
-                       enum intel_dpll_id pll_id);
+                       struct intel_dpll_hw_state *state);
 
 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
                                   int color_plane, unsigned int height);