x86/intel_idle: Add CPU model 0x4a (Atom Z34xx series)

Add CPU ID for Atom Z34xx processors. Datasheets indicate support for this,
detailed information about potential quirks or limitations are missing, though.
So we just reuse the definition from official BSP code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 4466a2f969d7ba5d5cafee13b7359047955cd07a..5ded9b22b01523580ccf88e9cf6498103609fc2e 100644 (file)
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -724,6 +724,50 @@ static struct cpuidle_state atom_cstates[] = {
        {
                .enter = NULL }
 };
+static struct cpuidle_state tangier_cstates[] = {
+       {
+               .name = "C1-TNG",
+               .desc = "MWAIT 0x00",
+               .flags = MWAIT2flg(0x00),
+               .exit_latency = 1,
+               .target_residency = 4,
+               .enter = &intel_idle,
+               .enter_freeze = intel_idle_freeze, },
+       {
+               .name = "C4-TNG",
+               .desc = "MWAIT 0x30",
+               .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 100,
+               .target_residency = 400,
+               .enter = &intel_idle,
+               .enter_freeze = intel_idle_freeze, },
+       {
+               .name = "C6-TNG",
+               .desc = "MWAIT 0x52",
+               .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 140,
+               .target_residency = 560,
+               .enter = &intel_idle,
+               .enter_freeze = intel_idle_freeze, },
+       {
+               .name = "C7-TNG",
+               .desc = "MWAIT 0x60",
+               .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 1200,
+               .target_residency = 4000,
+               .enter = &intel_idle,
+               .enter_freeze = intel_idle_freeze, },
+       {
+               .name = "C9-TNG",
+               .desc = "MWAIT 0x64",
+               .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
+               .exit_latency = 10000,
+               .target_residency = 20000,
+               .enter = &intel_idle,
+               .enter_freeze = intel_idle_freeze, },
+       {
+               .enter = NULL }
+};
 static struct cpuidle_state avn_cstates[] = {
        {
                .name = "C1-AVN",
@@ -978,6 +1022,10 @@ static const struct idle_cpu idle_cpu_atom = {
        .state_table = atom_cstates,
 };
 
+static const struct idle_cpu idle_cpu_tangier = {
+       .state_table = tangier_cstates,
+};
+
 static const struct idle_cpu idle_cpu_lincroft = {
        .state_table = atom_cstates,
        .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
@@ -1066,6 +1114,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
        ICPU(INTEL_FAM6_SANDYBRIDGE_X,          idle_cpu_snb),
        ICPU(INTEL_FAM6_ATOM_CEDARVIEW,         idle_cpu_atom),
        ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       idle_cpu_byt),
+       ICPU(INTEL_FAM6_ATOM_MERRIFIELD,        idle_cpu_tangier),
        ICPU(INTEL_FAM6_ATOM_AIRMONT,           idle_cpu_cht),
        ICPU(INTEL_FAM6_IVYBRIDGE,              idle_cpu_ivb),
        ICPU(INTEL_FAM6_IVYBRIDGE_X,            idle_cpu_ivt),