]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
firmware/qcom_scm: Add scm call to handle smmu errata
authorVivek Gautam <vivek.gautam@codeaurora.org>
Fri, 20 Sep 2019 08:04:28 +0000 (13:34 +0530)
committerWill Deacon <will@kernel.org>
Mon, 4 Nov 2019 17:48:37 +0000 (17:48 +0000)
Qcom's smmu-500 needs to toggle wait-for-safe sequence to
handle TLB invalidation sync's.
Few firmwares allow doing that through SCM interface.
Add API to toggle wait for safe from firmware through a
SCM call.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Andy Gross <agross@kernel.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Will Deacon <will@kernel.org>
drivers/firmware/qcom_scm-32.c
drivers/firmware/qcom_scm-64.c
drivers/firmware/qcom_scm.c
drivers/firmware/qcom_scm.h
include/linux/qcom_scm.h

index 215061c581e1f3c31099d623f4f43aefa31d03e9..bee8729525ec8f4ae3aa54138003aabb1163abeb 100644 (file)
@@ -614,3 +614,8 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
        return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
                                     addr, val);
 }
+
+int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
+{
+       return -ENODEV;
+}
index 872155c67b2dc711fb88634c504b7654e11caa1b..e1cd933ea9ae18277e340a25963f31394b7e5812 100644 (file)
@@ -552,3 +552,16 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
        return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
                             &desc, &res);
 }
+
+int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
+{
+       struct qcom_scm_desc desc = {0};
+       struct arm_smccc_res res;
+
+       desc.args[0] = QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL;
+       desc.args[1] = en;
+       desc.arginfo = QCOM_SCM_ARGS(2);
+
+       return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM,
+                                   QCOM_SCM_CONFIG_ERRATA1, &desc, &res);
+}
index 4802ab170fe51a57fb83f962bbf6f8a4b7936717..a729e05c21b8f380dab45b6c5dad54b894fcf8b7 100644 (file)
@@ -345,6 +345,12 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
 }
 EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
 
+int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
+{
+       return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
+}
+EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
+
 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
 {
        return __qcom_scm_io_readl(__scm->dev, addr, val);
index 99506bd873c0177897bf22320686a2ccc1643471..baee744dbcfe86a003aa4b464ace2a7ecd2d2c51 100644 (file)
@@ -91,10 +91,15 @@ extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
                                      u32 spare);
 #define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE        3
 #define QCOM_SCM_IOMMU_SECURE_PTBL_INIT        4
+#define QCOM_SCM_SVC_SMMU_PROGRAM      0x15
+#define QCOM_SCM_CONFIG_ERRATA1                0x3
+#define QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL     0x2
 extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
                                             size_t *size);
 extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
                                             u32 size, u32 spare);
+extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
+                                               bool enable);
 #define QCOM_MEM_PROT_ASSIGN_ID        0x16
 extern int  __qcom_scm_assign_mem(struct device *dev,
                                  phys_addr_t mem_region, size_t mem_sz,
index 2d5eff506e13b08924dd127ed7e8a13499780bae..ffd72b3b14eed4564514d5d83c6d0d47f58d2dc4 100644 (file)
@@ -58,6 +58,7 @@ extern int qcom_scm_set_remote_state(u32 state, u32 id);
 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
+extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
 extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
 extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
 #else
@@ -97,6 +98,7 @@ qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
 static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
 static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
 static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
+static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { return -ENODEV; }
 static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
 static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
 #endif