ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x

Use a generic name for this kind of PLL

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf0c845a6d5992b95b5f9ea124cf9bbd64a..d8b168ebd5f16d9ac351fe2ea856b28dc2c45437 100644 (file)
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
        "st,stih416-plls-c32-ddr",      "st,clkgen-plls-c32"
        "st,stih407-plls-c32-a0",       "st,clkgen-plls-c32"
        "st,stih407-plls-c32-a9",       "st,clkgen-plls-c32"
-       "st,stih407-plls-c32-c0_0",     "st,clkgen-plls-c32"
-       "st,stih407-plls-c32-c0_1",     "st,clkgen-plls-c32"
+       "sst,plls-c32-cx_0",            "st,clkgen-plls-c32"
+       "sst,plls-c32-cx_1",            "st,clkgen-plls-c32"
 
        "st,stih415-gpu-pll-c32",       "st,clkgengpu-pll-c32"
        "st,stih416-gpu-pll-c32",       "st,clkgengpu-pll-c32"

diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index e65744fc12ab0e293ae8d43ce1d05311f7216f10..ad45f5e8fac7b6ed158fae7768b4bda550fff61a 100644 (file)
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -134,7 +134,7 @@ clk_s_c0: clockgen-c@09103000 {
 
                        clk_s_c0_pll0: clk-s-c0-pll0 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;
 
@@ -143,7 +143,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
 
                        clk_s_c0_pll1: clk-s-c0-pll1 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;
 

diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 6b5803a30096f0bf4e64b18fd44d8bbb0221d24b..d1f2acafc9b69b833d989e01a1619aba161e5dff 100644 (file)
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
 
                        clk_s_c0_pll0: clk-s-c0-pll0 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;
 
@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
 
                        clk_s_c0_pll1: clk-s-c0-pll1 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;
 

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 0ab23daa28296f888d4b249d509690400be90eec..148e1772465f7f6f04995641f2b206d4de29eb10 100644 (file)
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -137,7 +137,7 @@ clk_s_c0: clockgen-c@09103000 {
 
                        clk_s_c0_pll0: clk-s-c0-pll0 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;
 
@@ -146,7 +146,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 {
 
                        clk_s_c0_pll1: clk-s-c0-pll1 {
                                #clock-cells = <1>;
-                               compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+                               compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
 
                                clocks = <&clk_sysin>;