]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
net: dsa: qca8k: disable delay for RGMII mode
authorVinod Koul <vkoul@kernel.org>
Mon, 21 Jan 2019 09:13:18 +0000 (14:43 +0530)
committerDavid S. Miller <davem@davemloft.net>
Wed, 23 Jan 2019 03:37:59 +0000 (19:37 -0800)
In RGMII mode we should not have any delay in port MAC, so disable
the delay.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/dsa/qca8k.c

index 7e97e620bd4476609663f3cb769e13f7f02ce479..a4b6cda380169868d7843fc0bf3af6b53ce57f1b 100644 (file)
@@ -420,7 +420,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
 static int
 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 {
-       u32 reg;
+       u32 reg, val;
 
        switch (port) {
        case 0:
@@ -439,17 +439,9 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
         */
        switch (mode) {
        case PHY_INTERFACE_MODE_RGMII:
-               qca8k_write(priv, reg,
-                           QCA8K_PORT_PAD_RGMII_EN |
-                           QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
-                           QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
-
-               /* According to the datasheet, RGMII delay is enabled through
-                * PORT5_PAD_CTRL for all ports, rather than individual port
-                * registers
-                */
-               qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
-                           QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
+               /* RGMII mode means no delay so don't enable the delay */
+               val = QCA8K_PORT_PAD_RGMII_EN;
+               qca8k_write(priv, reg, val);
                break;
        case PHY_INTERFACE_MODE_SGMII:
                qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);