ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface

The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index a92ac63addf070a6a63ce20d00593f04ff296345..b6f1e7a5e5ec0f9e00689f780d8d15378566573c 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -322,7 +322,10 @@ gic: interrupt-controller@1d00000 {
                                #interrupt-cells = <3>;
                                interrupt-controller;
                                reg = <0x1d00000 0x10000>, /* GICD */
-                                     <0x1d40000 0x40000>; /* GICR */
+                                     <0x1d40000 0x40000>, /* GICR */
+                                     <0x1d80000 0x2000>,  /* GICC */
+                                     <0x1d90000 0x2000>,  /* GICH */
+                                     <0x1da0000 0x20000>; /* GICV */
                                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                        };
                };