]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: tegra: migrate to new clock code
authorPrashant Gaikwad <pgaikwad@nvidia.com>
Fri, 11 Jan 2013 07:46:26 +0000 (13:16 +0530)
committerStephen Warren <swarren@nvidia.com>
Mon, 28 Jan 2013 18:19:07 +0000 (11:19 -0700)
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
21 files changed:
arch/arm/mach-tegra/board-dt-tegra20.c
arch/arm/mach-tegra/board-dt-tegra30.c
arch/arm/mach-tegra/clock.c
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/cpu-tegra.c
arch/arm/mach-tegra/include/mach/clk.h
arch/arm/mach-tegra/pcie.c
arch/arm/mach-tegra/powergate.c
drivers/clk/tegra/clk-periph.c
drivers/clk/tegra/clk.c
drivers/dma/tegra20-apb-dma.c
drivers/gpu/drm/tegra/dc.c
drivers/gpu/drm/tegra/drm.c
drivers/gpu/drm/tegra/hdmi.c
drivers/i2c/busses/i2c-tegra.c
drivers/input/keyboard/tegra-kbc.c
drivers/spi/spi-tegra20-sflash.c
drivers/spi/spi-tegra20-slink.c
drivers/staging/nvec/nvec.c
include/linux/clk/tegra.h
sound/soc/tegra/tegra30_ahub.c

index e1f87dd314ef101db3fa20618729750df9be3364..0c11b8af3af38b0d2ca71ea37d86729509beebc6 100644 (file)
@@ -42,7 +42,6 @@
 #include <asm/setup.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -104,37 +103,8 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
        {}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "uarta",      "pll_p",        216000000,      true },
-       { "uartd",      "pll_p",        216000000,      true },
-       { "usbd",       "clk_m",        12000000,       false },
-       { "usb2",       "clk_m",        12000000,       false },
-       { "usb3",       "clk_m",        12000000,       false },
-       { "pll_a",      "pll_p_out1",   56448000,       true },
-       { "pll_a_out0", "pll_a",        11289600,       true },
-       { "cdev1",      NULL,           0,              true },
-       { "blink",      "clk_32k",      32768,          true },
-       { "i2s1",       "pll_a_out0",   11289600,       false},
-       { "i2s2",       "pll_a_out0",   11289600,       false},
-       { "sdmmc1",     "pll_p",        48000000,       false},
-       { "sdmmc3",     "pll_p",        48000000,       false},
-       { "sdmmc4",     "pll_p",        48000000,       false},
-       { "spi",        "pll_p",        20000000,       false },
-       { "sbc1",       "pll_p",        100000000,      false },
-       { "sbc2",       "pll_p",        100000000,      false },
-       { "sbc3",       "pll_p",        100000000,      false },
-       { "sbc4",       "pll_p",        100000000,      false },
-       { "host1x",     "pll_c",        150000000,      false },
-       { "disp1",      "pll_p",        600000000,      false },
-       { "disp2",      "pll_p",        600000000,      false },
-       { NULL,         NULL,           0,              0},
-};
-
 static void __init tegra_dt_init(void)
 {
-       tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
        /*
         * Finished with the static registrations now; fill in the missing
         * devices
index cfe5fc02be775980e11866c25cd5d7fb655a8b75..92f6014d22a188b001c9860e6f9a62995b804cc3 100644 (file)
@@ -35,7 +35,6 @@
 #include <asm/hardware/gic.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -67,38 +66,8 @@ static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
        {}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "uarta",      "pll_p",        408000000,      true },
-       { "pll_a",      "pll_p_out1",   564480000,      true },
-       { "pll_a_out0", "pll_a",        11289600,       true },
-       { "extern1",    "pll_a_out0",   0,              true },
-       { "clk_out_1",  "extern1",      0,              true },
-       { "blink",      "clk_32k",      32768,          true },
-       { "i2s0",       "pll_a_out0",   11289600,       false},
-       { "i2s1",       "pll_a_out0",   11289600,       false},
-       { "i2s2",       "pll_a_out0",   11289600,       false},
-       { "i2s3",       "pll_a_out0",   11289600,       false},
-       { "i2s4",       "pll_a_out0",   11289600,       false},
-       { "sdmmc1",     "pll_p",        48000000,       false},
-       { "sdmmc3",     "pll_p",        48000000,       false},
-       { "sdmmc4",     "pll_p",        48000000,       false},
-       { "sbc1",       "pll_p",        100000000,      false},
-       { "sbc2",       "pll_p",        100000000,      false},
-       { "sbc3",       "pll_p",        100000000,      false},
-       { "sbc4",       "pll_p",        100000000,      false},
-       { "sbc5",       "pll_p",        100000000,      false},
-       { "sbc6",       "pll_p",        100000000,      false},
-       { "host1x",     "pll_c",        150000000,      false},
-       { "disp1",      "pll_p",        600000000,      false},
-       { "disp2",      "pll_p",        600000000,      false},
-       { NULL,         NULL,           0,              0},
-};
-
 static void __init tegra30_dt_init(void)
 {
-       tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
        of_platform_populate(NULL, of_default_bus_match_table,
                                tegra30_auxdata_lookup, NULL);
 }
index 8c0ff061f8cfb85a34ab019f66a073313becc62e..baa0c5b008f1bc649bc9d6d292fac0467025cc76 100644 (file)
@@ -31,9 +31,6 @@
 #include "board.h"
 #include "clock.h"
 
-/* Global data of Tegra CPU CAR ops */
-struct tegra_cpu_car_ops *tegra_cpu_car_ops;
-
 /*
  * Locking:
  *
@@ -131,22 +128,6 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
                tegra_clk_init_one_from_table(table);
 }
 
-void tegra_periph_reset_deassert(struct clk *c)
-{
-       struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-       BUG_ON(!clk->reset);
-       clk->reset(__clk_get_hw(c), false);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-       struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-       BUG_ON(!clk->reset);
-       clk->reset(__clk_get_hw(c), true);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
 /* Several extended clock configuration bits (e.g., clock routing, clock
  * phase control) are included in PLL and peripheral clock source
  * registers. */
index 3efe80b2af287697c99dc44c6245f66136ffdd0b..87dd69ccdf8e55ffe4747818d485424e9cc75b03 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/of_irq.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -29,7 +30,6 @@
 #include <mach/powergate.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
@@ -65,6 +65,7 @@ static const struct of_device_id tegra_dt_irq_match[] __initconst = {
 
 void __init tegra_dt_init_irq(void)
 {
+       tegra_clocks_init();
        tegra_init_irq();
        of_irq_init(tegra_dt_irq_match);
 }
@@ -80,43 +81,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
        writel_relaxed(reg, reset);
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "clk_m",      NULL,           0,              true },
-       { "pll_p",      "clk_m",        216000000,      true },
-       { "pll_p_out1", "pll_p",        28800000,       true },
-       { "pll_p_out2", "pll_p",        48000000,       true },
-       { "pll_p_out3", "pll_p",        72000000,       true },
-       { "pll_p_out4", "pll_p",        24000000,       true },
-       { "pll_c",      "clk_m",        600000000,      true },
-       { "pll_c_out1", "pll_c",        120000000,      true },
-       { "sclk",       "pll_c_out1",   120000000,      true },
-       { "hclk",       "sclk",         120000000,      true },
-       { "pclk",       "hclk",         60000000,       true },
-       { "csite",      NULL,           0,              true },
-       { "emc",        NULL,           0,              true },
-       { "cpu",        NULL,           0,              true },
-       { NULL,         NULL,           0,              0},
-};
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
-       /* name         parent          rate            enabled */
-       { "clk_m",      NULL,           0,              true },
-       { "pll_p",      "pll_ref",      408000000,      true },
-       { "pll_p_out1", "pll_p",        9600000,        true },
-       { "pll_p_out4", "pll_p",        102000000,      true },
-       { "sclk",       "pll_p_out4",   102000000,      true },
-       { "hclk",       "sclk",         102000000,      true },
-       { "pclk",       "hclk",         51000000,       true },
-       { "csite",      NULL,           0,              true },
-       { NULL,         NULL,           0,              0},
-};
-#endif
-
-
 static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -141,8 +105,6 @@ void __init tegra20_init_early(void)
        tegra_cpu_reset_handler_init();
        tegra_apb_io_init();
        tegra_init_fuse();
-       tegra2_init_clocks();
-       tegra_clk_init_from_table(tegra20_clk_init_table);
        tegra_init_cache();
        tegra_pmc_init();
        tegra_powergate_init();
@@ -155,8 +117,6 @@ void __init tegra30_init_early(void)
        tegra_cpu_reset_handler_init();
        tegra_apb_io_init();
        tegra_init_fuse();
-       tegra30_init_clocks();
-       tegra_clk_init_from_table(tegra30_clk_init_table);
        tegra_init_cache();
        tegra_pmc_init();
        tegra_powergate_init();
index 85d4a23bba039e1ce18372dcb283eea1a53f964c..ebffed67e2f5b6a60e0d83e6d4a7b097e9b56cbd 100644 (file)
@@ -266,7 +266,7 @@ static int __init tegra_cpufreq_init(void)
        if (IS_ERR(pll_x_clk))
                return PTR_ERR(pll_x_clk);
 
-       pll_p_clk = clk_get_sys(NULL, "pll_p");
+       pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
        if (IS_ERR(pll_p_clk))
                return PTR_ERR(pll_p_clk);
 
index 95f3a547c770a79a468017789ec8349b47d7471e..85bbf10a7d0d287876d9d49fd7b152aa64f4d2b5 100644 (file)
@@ -31,9 +31,6 @@ enum tegra_clk_ex_param {
        TEGRA_CLK_PLLD_MIPI_MUX_SEL,
 };
 
-void tegra_periph_reset_deassert(struct clk *c);
-void tegra_periph_reset_assert(struct clk *c);
-
 #ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
 #endif
index bffcd643d7a3eb14ef094d537444271344280a93..b60165f1ca02c56b76b78323a0d03119b871e9b8 100644 (file)
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/export.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/clk.h>
 #include <mach/powergate.h>
 
 #include "board.h"
index 2cc1185d902e38fd3678872c71ffc8320e89d383..c6bc8f85759c615a465dfe6bf7eaa8578bbcb84c 100644 (file)
@@ -26,8 +26,8 @@
 #include <linux/io.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
+#include <linux/clk/tegra.h>
 
-#include <mach/clk.h>
 #include <mach/powergate.h>
 
 #include "fuse.h"
index 5978e81b175b31e10a1dd5484cea9199a70f21e4..788486e6331a0f10fa99984f8f1b0581dfb90635 100644 (file)
@@ -110,6 +110,44 @@ static void clk_periph_disable(struct clk_hw *hw)
        gate_ops->disable(gate_hw);
 }
 
+void tegra_periph_reset_deassert(struct clk *c)
+{
+       struct clk_hw *hw = __clk_get_hw(c);
+       struct tegra_clk_periph *periph = to_clk_periph(hw);
+       struct tegra_clk_periph_gate *gate;
+
+       if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
+               gate = to_clk_periph_gate(hw);
+               if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
+                       WARN_ON(1);
+                       return;
+               }
+       } else {
+               gate = &periph->gate;
+       }
+
+       tegra_periph_reset(gate, 0);
+}
+
+void tegra_periph_reset_assert(struct clk *c)
+{
+       struct clk_hw *hw = __clk_get_hw(c);
+       struct tegra_clk_periph *periph = to_clk_periph(hw);
+       struct tegra_clk_periph_gate *gate;
+
+       if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
+               gate = to_clk_periph_gate(hw);
+               if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
+                       WARN_ON(1);
+                       return;
+               }
+       } else {
+               gate = &periph->gate;
+       }
+
+       tegra_periph_reset(gate, 1);
+}
+
 const struct clk_ops tegra_clk_periph_ops = {
        .get_parent = clk_periph_get_parent,
        .set_parent = clk_periph_set_parent,
index cf023a93720810d882a41403a934ab1d8fd45bd8..a603b9af0ad38cda8ca3ee590174909dcaea2994 100644 (file)
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/clk/tegra.h>
 
 #include "clk.h"
 
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
                                struct clk *clks[], int clk_max)
 {
@@ -67,3 +72,14 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
                        }
        }
 }
+
+static const struct of_device_id tegra_dt_clk_match[] = {
+       { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
+       { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
+       { }
+};
+
+void __init tegra_clocks_init(void)
+{
+       of_clk_init(tegra_dt_clk_match);
+}
index c39e61bc8172e5c277dfd4cdb0997cfcc08e407f..afc9b89e20f4c9d22c0eb251a1f6b426bef844ca 100644 (file)
@@ -31,8 +31,8 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/slab.h>
+#include <linux/clk/tegra.h>
 
-#include <mach/clk.h>
 #include "dmaengine.h"
 
 #define TEGRA_APBDMA_GENERAL                   0x0
index 656b2e3334a621109426806043032ae3422d9631..56813f967c8f97d0b8a601f359b65f1d6a2af65d 100644 (file)
@@ -12,8 +12,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #include "drm.h"
 #include "dc.h"
index 3a503c9e468649c0b9869b0d0385abc736af4650..d980dc75788c1515258698c5457a02be7e4cf794 100644 (file)
@@ -11,7 +11,6 @@
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 
-#include <mach/clk.h>
 #include <linux/dma-mapping.h>
 #include <asm/dma-iommu.h>
 
index e060c7e6434dba886e8698782cbfb0c3ce4b9cf7..92ad276cc5e075d8ea4cb9f0d1087bb22d77fb5b 100644 (file)
@@ -14,8 +14,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
-
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #include "hdmi.h"
 #include "drm.h"
index 7b38877ffec10ed06995b191a024871c9c1e923d..c7aca35e38fdd7dc10ded8402de85e607ed283f2 100644 (file)
 #include <linux/of_i2c.h>
 #include <linux/of_device.h>
 #include <linux/module.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/unaligned.h>
 
-#include <mach/clk.h>
-
 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
 #define BYTES_PER_FIFO_WORD 4
 
index c76f96872d313f558eb9a75e6305a7d14e123d2c..54ac1dc7d477b4cdcb22e2188233a2ae6b79c01f 100644 (file)
@@ -30,7 +30,7 @@
 #include <linux/clk.h>
 #include <linux/slab.h>
 #include <linux/input/tegra_kbc.h>
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #define KBC_MAX_DEBOUNCE_CNT   0x3ffu
 
index 448a8cc71df3aef818a0a0d4d0058e2c47cabf68..02feaa51a0fa0f971f416291a11ae4d8ad712be2 100644 (file)
@@ -34,7 +34,7 @@
 #include <linux/of_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-tegra.h>
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #define SPI_COMMAND                            0x000
 #define SPI_GO                                 BIT(30)
index 651167f2e0afbafbeab8ded7fac067923d41f910..fa208a5cc612b89dc1f9aaa944ad094cdf85d508 100644 (file)
@@ -35,7 +35,7 @@
 #include <linux/of_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-tegra.h>
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #define SLINK_COMMAND                  0x000
 #define SLINK_BIT_LENGTH(x)            (((x) & 0x1f) << 0)
index 2830946860d11e91d373b547c6050c076bf1f014..d51615b1979714197f68d8b1f535e8637ce7561b 100644 (file)
@@ -37,8 +37,7 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
-
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 
 #include "nvec.h"
 
index 0977f2a247579d39e8deae17eed52969a44ce68b..a7e5a39990993cf322d62f03a57a55171e00b89a 100644 (file)
@@ -17,6 +17,8 @@
 #ifndef __LINUX_CLK_TEGRA_H_
 #define __LINUX_CLK_TEGRA_H_
 
+#include <linux/clk.h>
+
 /*
  * Tegra CPU clock and reset control ops
  *
@@ -120,5 +122,8 @@ static inline void tegra_cpu_clock_resume(void)
 
 void tegra20_cpu_car_ops_init(void);
 void tegra30_cpu_car_ops_init(void);
+void tegra_periph_reset_deassert(struct clk *c);
+void tegra_periph_reset_assert(struct clk *c);
+void tegra_clocks_init(void);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
index f354dc390a0be4c1b57ae473f8b357f9c66cb632..bb31c4123a7bbb51a3bb1e936d2181ad464fbe5b 100644 (file)
@@ -25,7 +25,7 @@
 #include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
-#include <mach/clk.h>
+#include <linux/clk/tegra.h>
 #include <sound/soc.h>
 #include "tegra30_ahub.h"