ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry

Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 8d102d31021257295445e75bb3aaf003afbb109c..04da5eac83768de800fce1f453e3062d114131de 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -603,6 +603,21 @@ ocram: sram@ffe00000 {
                        reg = <0xffe00000 0x40000>;
                };
 
+               eccmgr: eccmgr@ffd06000 {
+                       compatible = "altr,socfpga-a10-ecc-manager";
+                       altr,sysmgr-syscon = <&sysmgr>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <0 0 IRQ_TYPE_LEVEL_HIGH>;
+                       ranges;
+
+                       l2-ecc@ffd06010 {
+                               compatible = "altr,socfpga-a10-l2-ecc";
+                               reg = <0xffd06010 0x4>;
+                       };
+               };
+
                rst: rstmgr@ffd05000 {
                        #reset-cells = <1>;
                        compatible = "altr,rst-mgr";