]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: sun8i: v3s: Fix the RTC node
authorMaxime Ripard <maxime.ripard@bootlin.com>
Sat, 25 May 2019 13:09:19 +0000 (15:09 +0200)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Thu, 6 Jun 2019 10:56:01 +0000 (12:56 +0200)
For some reason, while the v3s has a dedicated compatible in the RTC
binding, the one actually used was the A31's. However, it turns out that
the controller is pretty different (which justified the compatible).

Let's use the proper compatible, and use the proper binding description as
well.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
arch/arm/boot/dts/sun8i-v3s.dtsi

index df72b1719c341241b9170fd7c763e9c1dbfe67f9..6ba9377458b3431c8d9f4c8f2f5e4f20ababa108 100644 (file)
@@ -91,7 +91,7 @@ osc32k: osc32k_clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <32768>;
-                       clock-output-names = "osc32k";
+                       clock-output-names = "ext-osc32k";
                };
        };
 
@@ -264,17 +264,20 @@ usbphy: phy@1c19400 {
                ccu: clock@1c20000 {
                        compatible = "allwinner,sun8i-v3s-ccu";
                        reg = <0x01c20000 0x400>;
-                       clocks = <&osc24M>, <&osc32k>;
+                       clocks = <&osc24M>, <&rtc 0>;
                        clock-names = "hosc", "losc";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };
 
                rtc: rtc@1c20400 {
-                       compatible = "allwinner,sun6i-a31-rtc";
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun8i-v3-rtc";
                        reg = <0x01c20400 0x54>;
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&osc32k>;
+                       clock-output-names = "osc32k", "osc32k-out";
                };
 
                pio: pinctrl@1c20800 {
@@ -282,7 +285,7 @@ pio: pinctrl@1c20800 {
                        reg = <0x01c20800 0x400>;
                        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+                       clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
                        clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        #gpio-cells = <3>;