struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct dce_hwseq *hws = dc->hwseq;
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
+
power_on_plane(dc->hwseq,
pipe_ctx->pipe_idx);
pipe_ctx->plane_res.scl_data.recout.y);
print_rq_dlg_ttu(dc, pipe_ctx);
}
+
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
}
static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
{
struct dm_pp_clock_for_voltage_req clock;
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
+
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
return;
}
dcn10_pplib_apply_display_requirements(dc, context);
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
+
/* need to fix this function. not doing the right thing here */
}
{
int i;
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
+
if (!pipe_ctx->stream_res.opp)
return;
}
}
+ if (dc->public.debug.sanity_checks) {
+ verify_allow_pstate_change_high(dc->hwseq);
+ }
+
}
static bool dcn10_dummy_display_power_gating(