mips: annotate implicit fall throughs

There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings. Fix them up.

This patch produces no change in behaviour, but should be reviewed in
case these are actually bugs not intentional fallthoughs.

Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Kees Cook <keescook@google.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 2077a4dce7637861318b2d70723702111362d46e..180ad081afcf932fe61c7431bc1b87f5ebb1cc9d 100644 (file)
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -451,6 +451,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                case bltzl_op:
                        if (NO_R6EMU)
                                goto sigill_r2r6;
+                       /* fall through */
                case bltz_op:
                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -464,6 +465,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                case bgezl_op:
                        if (NO_R6EMU)
                                goto sigill_r2r6;
+                       /* fall through */
                case bgez_op:
                        if ((long)regs->regs[insn.i_format.rs] >= 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
@@ -559,6 +561,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case jalx_op:
        case jal_op:
                regs->regs[31] = regs->cp0_epc + 8;
+               /* fall through */
        case j_op:
                epc += 4;
                epc >>= 28;
@@ -575,6 +578,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case beql_op:
                if (NO_R6EMU)
                        goto sigill_r2r6;
+               /* fall through */
        case beq_op:
                if (regs->regs[insn.i_format.rs] ==
                    regs->regs[insn.i_format.rt]) {
@@ -589,6 +593,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case bnel_op:
                if (NO_R6EMU)
                        goto sigill_r2r6;
+               /* fall through */
        case bne_op:
                if (regs->regs[insn.i_format.rs] !=
                    regs->regs[insn.i_format.rt]) {
@@ -603,6 +608,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case blezl_op: /* not really i_format */
                if (!insn.i_format.rt && NO_R6EMU)
                        goto sigill_r2r6;
+               /* fall through */
        case blez_op:
                /*
                 * Compact branches for R6 for the
@@ -638,6 +644,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
        case bgtzl_op:
                if (!insn.i_format.rt && NO_R6EMU)
                        goto sigill_r2r6;
+               /* fall through */
        case bgtz_op:
                /*
                 * Compact branches for R6 for the

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 65dc2e699a2ec10597c54b8b159a6f9367fee0a1..95b18a194f53797f9be7a4f8552b382a2600ee00 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -517,12 +517,16 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
        switch (isa) {
        case MIPS_CPU_ISA_M64R2:
                c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
+               /* fall through */
        case MIPS_CPU_ISA_M64R1:
                c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
+               /* fall through */
        case MIPS_CPU_ISA_V:
                c->isa_level |= MIPS_CPU_ISA_V;
+               /* fall through */
        case MIPS_CPU_ISA_IV:
                c->isa_level |= MIPS_CPU_ISA_IV;
+               /* fall through */
        case MIPS_CPU_ISA_III:
                c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
                break;
@@ -530,14 +534,17 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
        /* R6 incompatible with everything else */
        case MIPS_CPU_ISA_M64R6:
                c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
+               /* fall through */
        case MIPS_CPU_ISA_M32R6:
                c->isa_level |= MIPS_CPU_ISA_M32R6;
                /* Break here so we don't add incompatible ISAs */
                break;
        case MIPS_CPU_ISA_M32R2:
                c->isa_level |= MIPS_CPU_ISA_M32R2;
+               /* fall through */
        case MIPS_CPU_ISA_M32R1:
                c->isa_level |= MIPS_CPU_ISA_M32R1;
+               /* fall through */
        case MIPS_CPU_ISA_II:
                c->isa_level |= MIPS_CPU_ISA_II;
                break;

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index 0e61a5b7647f2d18cbb88558d3319f729f0699b2..ba73b407766885b0fb311c618b055f473a4aacd6 100644 (file)
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -27,12 +27,15 @@ void mips_install_watch_registers(struct task_struct *t)
        case 4:
                write_c0_watchlo3(watches->watchlo[3]);
                write_c0_watchhi3(watchhi | watches->watchhi[3]);
+               /* fall through */
        case 3:
                write_c0_watchlo2(watches->watchlo[2]);
                write_c0_watchhi2(watchhi | watches->watchhi[2]);
+               /* fall through */
        case 2:
                write_c0_watchlo1(watches->watchlo[1]);
                write_c0_watchhi1(watchhi | watches->watchhi[1]);
+               /* fall through */
        case 1:
                write_c0_watchlo0(watches->watchlo[0]);
                write_c0_watchhi0(watchhi | watches->watchhi[0]);
@@ -55,10 +58,13 @@ void mips_read_watch_registers(void)
                BUG();
        case 4:
                watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask);
+               /* fall through */
        case 3:
                watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask);
+               /* fall through */
        case 2:
                watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask);
+               /* fall through */
        case 1:
                watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask);
        }
@@ -85,18 +91,25 @@ void mips_clear_watch_registers(void)
                BUG();
        case 8:
                write_c0_watchlo7(0);
+               /* fall through */
        case 7:
                write_c0_watchlo6(0);
+               /* fall through */
        case 6:
                write_c0_watchlo5(0);
+               /* fall through */
        case 5:
                write_c0_watchlo4(0);
+               /* fall through */
        case 4:
                write_c0_watchlo3(0);
+               /* fall through */
        case 3:
                write_c0_watchlo2(0);
+               /* fall through */
        case 2:
                write_c0_watchlo1(0);
+               /* fall through */
        case 1:
                write_c0_watchlo0(0);
        }

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 96d666a0f4a070fdcddb1c347db07c0aec765c65..d0b64df51eb284feeaa8028e79a1468b1eefa565 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1280,6 +1280,7 @@ static void probe_pcache(void)
 
        case CPU_VR4133:
                write_c0_config(config & ~VR41_CONF_P4K);
+               /* fall through */
        case CPU_VR4131:
                /* Workaround for cache instruction bug of VR4131 */
                if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
@@ -1527,6 +1528,7 @@ static void probe_pcache(void)
                        c->dcache.flags |= MIPS_CACHE_PINDEX;
                        break;
                }
+               /* fall through */
        default:
                if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
                        c->dcache.flags |= MIPS_CACHE_ALIASES;

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 06771429164317c3e8bfe5da8e02e33445fb0b14..37b1cb246332298bd612cd841352093e6323fa49 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -576,6 +576,7 @@ void build_tlb_write_entry(u32 **p, struct uasm_label **l,
        case CPU_R5500:
                if (m4kc_tlbp_war())
                        uasm_i_nop(p);
+               /* fall through */
        case CPU_ALCHEMY:
                tlbw(p);
                break;