drm/amdgpu/soc15: add support for vega12

Add the IP blocks, clock and powergating flags, and
common clockgating support.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 242c30b72b10909f17bb68684fee858ad62b1b9b..91b0ef579c75b7f4c7185a86f0114d424f211f86 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -527,6 +527,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_VEGA10:
+       case CHIP_VEGA12:
                amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
                amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
                amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
@@ -651,6 +652,11 @@ static int soc15_common_early_init(void *handle)
                adev->pg_flags = 0;
                adev->external_rev_id = 0x1;
                break;
+       case CHIP_VEGA12:
+               adev->cg_flags = 0;
+               adev->pg_flags = 0;
+               adev->external_rev_id = 0x1; /* ??? */
+               break;
        case CHIP_RAVEN:
                adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                        AMD_CG_SUPPORT_GFX_MGLS |
@@ -883,6 +889,7 @@ static int soc15_common_set_clockgating_state(void *handle,
 
        switch (adev->asic_type) {
        case CHIP_VEGA10:
+       case CHIP_VEGA12:
                adev->nbio_funcs->update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE ? true : false);
                adev->nbio_funcs->update_medium_grain_light_sleep(adev,