clk: meson: add the gxl hdmi pll

The hdmi pll used in the gxl family is actually different from the gxbb
one. The register layout is completely different, which explain why the
hdmi pll rate has always been rubbish on the gxl family.

Adding the correct register field is the first part of the fix to get a
correct rate out the hdmi pll

Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index e83573b457fcb0d818ac7b5c06c355cdf26f3021..de1cea7a47fbbf8eee81b7743f9e9a0d4fa876b1 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -253,6 +253,52 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
        },
 };
 
+static struct meson_clk_pll gxl_hdmi_pll = {
+       .m = {
+               .reg_off = HHI_HDMI_PLL_CNTL,
+               .shift   = 0,
+               .width   = 9,
+       },
+       .n = {
+               .reg_off = HHI_HDMI_PLL_CNTL,
+               .shift   = 9,
+               .width   = 5,
+       },
+       .frac = {
+               /*
+                * On gxl, there is a register shift due to HHI_HDMI_PLL_CNTL1
+                * which does not exist on gxbb, so we compute the register
+                * offset based on the PLL base to get it right
+                */
+               .reg_off = HHI_HDMI_PLL_CNTL + 4,
+               .shift   = 0,
+               .width   = 12,
+       },
+       .od = {
+               .reg_off = HHI_HDMI_PLL_CNTL + 8,
+               .shift   = 21,
+               .width   = 2,
+       },
+       .od2 = {
+               .reg_off = HHI_HDMI_PLL_CNTL + 8,
+               .shift   = 23,
+               .width   = 2,
+       },
+       .od3 = {
+               .reg_off = HHI_HDMI_PLL_CNTL + 8,
+               .shift   = 19,
+               .width   = 2,
+       },
+       .lock = &meson_clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "hdmi_pll",
+               .ops = &meson_clk_pll_ro_ops,
+               .parent_names = (const char *[]){ "xtal" },
+               .num_parents = 1,
+               .flags = CLK_GET_RATE_NOCACHE,
+       },
+};
+
 static struct meson_clk_pll gxbb_sys_pll = {
        .m = {
                .reg_off = HHI_SYS_PLL_CNTL,
@@ -1520,7 +1566,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
        .hws = {
                [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
-               [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
+               [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
                [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
                [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
                [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
@@ -1675,7 +1721,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = {
 
 static struct meson_clk_pll *const gxl_clk_plls[] = {
        &gxbb_fixed_pll,
-       &gxbb_hdmi_pll,
+       &gxl_hdmi_pll,
        &gxbb_sys_pll,
        &gxl_gp0_pll,
 };