arm64: tegra: Add L2 cache topology to Tegra210

Add L2 cache and make it the next level of cache for each of the CPUs.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 79cedd36ffad972fcc33c06af3f2a6fc10308ca8..a550c0a4d572fd7360e33c1bb64518c2939965e8 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1372,6 +1372,7 @@ cpu@0 {
                        clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
                        clock-latency = <300000>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@1 {
@@ -1379,6 +1380,7 @@ cpu@1 {
                        compatible = "arm,cortex-a57";
                        reg = <1>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@2 {
@@ -1386,6 +1388,7 @@ cpu@2 {
                        compatible = "arm,cortex-a57";
                        reg = <2>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                cpu@3 {
@@ -1393,6 +1396,7 @@ cpu@3 {
                        compatible = "arm,cortex-a57";
                        reg = <3>;
                        cpu-idle-states = <&CPU_SLEEP>;
+                       next-level-cache = <&L2>;
                };
 
                idle-states {
@@ -1409,6 +1413,10 @@ CPU_SLEEP: cpu-sleep {
                                status = "disabled";
                        };
                };
+
+               L2: l2-cache {
+                       compatible = "cache";
+               };
        };
 
        timer {