]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/i915: Kill INTEL_SUBPLATFORM_AML
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 5 Jun 2019 16:29:46 +0000 (19:29 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 12 Jun 2019 11:51:26 +0000 (14:51 +0300)
All AML parts are either KBL ULX or CFL ULX so there is no point
in keeping INTEL_SUBPLATFORM_AML around. As these are the only
CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just
replace IS_AML_ULX with IS_CFL_ULX (it was already paired with
IS_KBL_ULX which accounts for the other half of the AML parts).

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190605162946.19223-2-ville.syrjala@linux.intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_ddi.c
drivers/gpu/drm/i915/intel_device_info.c
drivers/gpu/drm/i915/intel_device_info.h

index 2e2cfbfa0ceddb2e3d40a9e78d13dc49ecf2d7d0..caf999180d57fc0824ada6927b3eec127ccdc571 100644 (file)
@@ -2223,9 +2223,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
        IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
 #define IS_KBL_ULX(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_AML_ULX(dev_priv) \
-       (IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
-        IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
 #define IS_SKL_GT2(dev_priv)   (IS_SKYLAKE(dev_priv) && \
                                 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_SKL_GT3(dev_priv)   (IS_SKYLAKE(dev_priv) && \
@@ -2238,6 +2235,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
                                 INTEL_INFO(dev_priv)->gt == 3)
 #define IS_CFL_ULT(dev_priv) \
        IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_CFL_ULX(dev_priv) \
+       IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
 #define IS_CFL_GT2(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
                                 INTEL_INFO(dev_priv)->gt == 2)
 #define IS_CFL_GT3(dev_priv)   (IS_COFFEELAKE(dev_priv) && \
index 2fad62099ca5c2ad9cacc229b6202c357430b7d7..7925a176f90073763bf189cb0bee2482b8cf5c94 100644 (file)
@@ -615,7 +615,7 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 static const struct ddi_buf_trans *
 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
 {
-       if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+       if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
                *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
                return kbl_y_ddi_translations_dp;
        } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
@@ -631,7 +631,8 @@ static const struct ddi_buf_trans *
 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 {
        if (dev_priv->vbt.edp.low_vswing) {
-               if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+               if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
+                   IS_CFL_ULX(dev_priv)) {
                        *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
                        return skl_y_ddi_translations_edp;
                } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
@@ -653,7 +654,8 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 static const struct ddi_buf_trans *
 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 {
-       if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
+       if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
+           IS_CFL_ULX(dev_priv)) {
                *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
                return skl_y_ddi_translations_hdmi;
        } else {
index 19437e8ec6fa47c2108539cb9820feff94ef95e3..7135d8dc32a78a47540f15cdea56591ceb4a89fc 100644 (file)
@@ -787,9 +787,6 @@ static const u16 subplatform_ulx_ids[] = {
        INTEL_SKL_ULX_GT2_IDS(0),
        INTEL_KBL_ULX_GT1_IDS(0),
        INTEL_KBL_ULX_GT2_IDS(0),
-};
-
-static const u16 subplatform_aml_ids[] = {
        INTEL_AML_KBL_GT2_IDS(0),
        INTEL_AML_CFL_GT2_IDS(0),
 };
@@ -832,9 +829,6 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
                        /* ULX machines are also considered ULT. */
                        mask |= BIT(INTEL_SUBPLATFORM_ULT);
                }
-       } else if (find_devid(devid, subplatform_aml_ids,
-                             ARRAY_SIZE(subplatform_aml_ids))) {
-               mask = BIT(INTEL_SUBPLATFORM_AML);
        } else if (find_devid(devid, subplatform_portf_ids,
                              ARRAY_SIZE(subplatform_portf_ids))) {
                mask = BIT(INTEL_SUBPLATFORM_PORTF);
index 1fb8b50df7dfc534fb1ea09e356dd0bdb3640d74..3ea953a230b3f9948469b53b1110ca770bb0b502 100644 (file)
@@ -91,7 +91,6 @@ enum intel_platform {
 /* HSW/BDW/SKL/KBL/CFL */
 #define INTEL_SUBPLATFORM_ULT  (0)
 #define INTEL_SUBPLATFORM_ULX  (1)
-#define INTEL_SUBPLATFORM_AML  (2)
 
 /* CNL/ICL */
 #define INTEL_SUBPLATFORM_PORTF        (0)