drm/amd/display: Update min dcfclk

[Why]
NV12 has lower min dcfclk

[How]
Add update in update_bounding_box

Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2596d4ac6263b660892c40e3ea8ad700224af3a2..25515c255a3d2fc1eeee786c8bf90cefb5f57acd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3084,10 +3084,14 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 
        if (dc->bb_overrides.min_dcfclk_mhz > 0)
                min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
-       else
-               // Accounting for SOC/DCF relationship, we can go as high as
-               // 506Mhz in Vmin.  We need to code 507 since SMU will round down to 506.
-               min_dcfclk = 507;
+       else {
+               if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
+                       min_dcfclk = 310;
+               else
+                       // Accounting for SOC/DCF relationship, we can go as high as
+                       // 506Mhz in Vmin.
+                       min_dcfclk = 506;
+       }
 
        for (i = 0; i < num_states; i++) {
                int min_fclk_required_by_uclk;