media: Fix Lane mapping in Cadence CSI2TX

This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>

diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index 232259c71adf76c0a0b3539dc8ac9d299221e90b..c72c8a0654286d3cedce01abbb7a3c8b6fd82e6b 100644 (file)
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
        /* Put our lanes (clock and data) out of reset */
        reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
        for (i = 0; i < csi2tx->num_lanes; i++)
-               reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
+               reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
        writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
 
        udelay(10);
@@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
        /* Enable our (clock and data) lanes */
        reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
        for (i = 0; i < csi2tx->num_lanes; i++)
-               reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
+               reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
        writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
 
        udelay(10);