MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLB

For MIPS32R3 supported cores, the EHINV bit needs to be set when
invalidating the TLB. This is necessary because the legacy software
method of representing an invalid TLB entry using an unmapped address
value is not guaranteed to work.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6132/

diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index 235367cec4e63be3a3f5d347122ac5540f80c48c..4a2349302b552c5a7c4772c235553b4bdbef4695 100644 (file)
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -18,7 +18,9 @@
  */
 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
 
-#define UNIQUE_ENTRYHI(idx)    (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+#define UNIQUE_ENTRYHI(idx)                                            \
+               ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) |               \
+                (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
 
 #include <asm-generic/tlb.h>