]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: r8a7743: Add MSIOF[012] support
authorFabrizio Castro <fabrizio.castro@bp.renesas.com>
Wed, 27 Sep 2017 09:57:04 +0000 (10:57 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Thu, 28 Sep 2017 06:02:04 +0000 (08:02 +0200)
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi.
Also, define aliases for spi[123].

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7743.dtsi

index 454f98060d6f3c7b5bd7a98b82e1d0bd4518c23b..d541fd9ffafb34ce653fbce3feb041c5ae0ad72a 100644 (file)
@@ -29,6 +29,9 @@ aliases {
                i2c7 = &iic1;
                i2c8 = &iic3;
                spi0 = &qspi;
+               spi1 = &msiof0;
+               spi2 = &msiof1;
+               spi3 = &msiof2;
        };
 
        cpus {
@@ -852,6 +855,54 @@ qspi: spi@e6b10000 {
                        status = "disabled";
                };
 
+               msiof0: spi@e6e20000 {
+                       compatible = "renesas,msiof-r8a7743",
+                                    "renesas,rcar-gen2-msiof";
+                       reg = <0 0xe6e20000 0 0x0064>;
+                       interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 000>;
+                       dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                              <&dmac1 0x51>, <&dmac1 0x52>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       resets = <&cpg 000>;
+                       status = "disabled";
+               };
+
+               msiof1: spi@e6e10000 {
+                       compatible = "renesas,msiof-r8a7743",
+                                    "renesas,rcar-gen2-msiof";
+                       reg = <0 0xe6e10000 0 0x0064>;
+                       interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 208>;
+                       dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                              <&dmac1 0x55>, <&dmac1 0x56>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       resets = <&cpg 208>;
+                       status = "disabled";
+               };
+
+               msiof2: spi@e6e00000 {
+                       compatible = "renesas,msiof-r8a7743",
+                                    "renesas,rcar-gen2-msiof";
+                       reg = <0 0xe6e00000 0 0x0064>;
+                       interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 205>;
+                       dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                              <&dmac1 0x41>, <&dmac1 0x42>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       resets = <&cpg 205>;
+                       status = "disabled";
+               };
+
                sdhi0: sd@ee100000 {
                        compatible = "renesas,sdhi-r8a7743";
                        reg = <0 0xee100000 0 0x328>;