]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings: phy: qcom-ufs: Add resets property
authorEvan Green <evgreen@chromium.org>
Thu, 21 Mar 2019 17:17:55 +0000 (10:17 -0700)
committerKishon Vijay Abraham I <kishon@ti.com>
Wed, 17 Apr 2019 08:42:54 +0000 (14:12 +0530)
Add a resets property to the PHY that represents the PHY reset
register in the UFS controller itself. This better describes the
complete specification of the PHY, and allows the PHY to perform
its initialization in a single function, rather than relying on
back-channel sequencing of initialization through the PHY framework.

Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Documentation/devicetree/bindings/ufs/ufs-qcom.txt

index 21d9a93db2e970cde487151f667c93063a8ae5f9..fd59f93e95562f2d42828be1a9a1c6ebed2eccf8 100644 (file)
@@ -29,6 +29,7 @@ Optional properties:
 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
 - vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply
 - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply
+- resets : specifies the PHY reset in the UFS controller
 
 Example:
 
@@ -51,9 +52,11 @@ Example:
                        <&clock_gcc clk_ufs_phy_ldo>,
                        <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
                        <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
+               resets = <&ufshc 0>;
        };
 
-       ufshc@fc598000 {
+       ufshc: ufshc@fc598000 {
+               #reset-cells = <1>;
                ...
                phys = <&ufsphy1>;
                phy-names = "ufsphy";