drm/amd/display: update dml related structs

In preparation for further changes

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index f7f1f58fa65526f1d0ea380c242adc94c9098397..cfc69919ef9e45c725e071ae576e3cad3418a63a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2033,6 +2033,7 @@ int dcn20_populate_dml_pipes_from_context(
                        pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
                        if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
                                pipes[pipe_cnt].pipe.src.viewport_height = 1080;
+                       pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
                        pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
                        pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
                        pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
@@ -2066,6 +2067,7 @@ int dcn20_populate_dml_pipes_from_context(
                        pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
                        pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
                        pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
+                       pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
                        if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
                                pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
                                pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 516396d53d01dd5b9ed45053dc15cb3b33e7a7ad..220d5e610f1f5812186040c4965ade41229de988 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -99,6 +99,7 @@ struct _vcs_dpi_soc_bounding_box_st {
        unsigned int num_chans;
        unsigned int vmm_page_size_bytes;
        unsigned int hostvm_min_page_size_bytes;
+       unsigned int gpuvm_min_page_size_bytes;
        double dram_clock_change_latency_us;
        double dummy_pstate_latency_us;
        double writeback_dram_clock_change_latency_us;
@@ -224,6 +225,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
        int source_scan;
        int sw_mode;
        int macro_tile_size;
+       unsigned int surface_height_y;
        unsigned int viewport_width;
        unsigned int viewport_height;
        unsigned int viewport_y_y;
@@ -400,6 +402,7 @@ struct _vcs_dpi_display_rq_misc_params_st {
 struct _vcs_dpi_display_rq_params_st {
        unsigned char yuv420;
        unsigned char yuv420_10bpc;
+       unsigned char rgbe_alpha;
        display_rq_misc_params_st misc;
        display_rq_sizing_params_st sizing;
        display_rq_dlg_params_st dlg;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index b1c2b79e42b63fd631a72a8c2d392e03005f441d..15b72a8b5174f5759eb892bbb5d04fdfd9371373 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -231,7 +231,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
        mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading = soc->dcn_downspread_percent;   // new
        mode_lib->vba.DISPCLKDPPCLKVCOSpeed = soc->dispclk_dppclk_vco_speed_mhz;   // new
        mode_lib->vba.VMMPageSize = soc->vmm_page_size_bytes;
-       mode_lib->vba.GPUVMMinPageSize = soc->vmm_page_size_bytes / 1024;
+       mode_lib->vba.GPUVMMinPageSize = soc->gpuvm_min_page_size_bytes / 1024;
        mode_lib->vba.HostVMMinPageSize = soc->hostvm_min_page_size_bytes / 1024;
        // Set the voltage scaling clocks as the defaults. Most of these will
        // be set to different values by the test