]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: marvell: mcbin: enable more networking ports
authorAntoine Tenart <antoine.tenart@free-electrons.com>
Thu, 24 Aug 2017 08:46:39 +0000 (10:46 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Wed, 30 Aug 2017 09:37:06 +0000 (11:37 +0200)
This patch enables the two GE/SFP ports. They are configured in 10GKR
mode by default. To do this the cpm_xdmio is enabled as well, and two
phy descriptions are added.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts

index 21fb721be6cb91f3da5cc9cc2a454772f8f7cb8f..acf5c7d16d79b2f07eedf4691a1fc820073c7ffc 100644 (file)
@@ -202,6 +202,30 @@ cpm_sdhci_pins: sdhci-pins {
        };
 };
 
+&cpm_xmdio {
+       status = "okay";
+
+       phy0: ethernet-phy@0 {
+               compatible = "ethernet-phy-ieee802.3-c45";
+               reg = <0>;
+       };
+
+       phy8: ethernet-phy@8 {
+               compatible = "ethernet-phy-ieee802.3-c45";
+               reg = <8>;
+       };
+};
+
+&cpm_ethernet {
+       status = "okay";
+};
+
+&cpm_eth0 {
+       status = "okay";
+       phy = <&phy0>;
+       phy-mode = "10gbase-kr";
+};
+
 &cpm_sata0 {
        /* CPM Lane 0 - U29 */
        status = "okay";
@@ -231,6 +255,12 @@ &cps_ethernet {
        status = "okay";
 };
 
+&cps_eth0 {
+       status = "okay";
+       phy = <&phy8>;
+       phy-mode = "10gbase-kr";
+};
+
 &cps_eth1 {
        /* CPS Lane 0 - J5 (Gigabit RJ45) */
        status = "okay";