BAR2 being done for practical reasons, this is just for consistency.
Flushes have been added after the write to bind the instance block,
as later commits will reveal the need for them.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
nvkm_bar_init(struct nvkm_subdev *subdev)
{
struct nvkm_bar *bar = nvkm_bar(subdev);
+ bar->func->bar1.init(bar);
+ bar->func->bar1.wait(bar);
bar->func->init(bar);
return 0;
}
.dtor = nv50_bar_dtor,
.oneinit = nv50_bar_oneinit,
.init = nv50_bar_init,
+ .bar1.init = nv50_bar_bar1_init,
+ .bar1.wait = nv50_bar_bar1_wait,
.kmap = nv50_bar_kmap,
.umap = nv50_bar_umap,
.flush = g84_bar_flush,
return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);
}
+void
+gf100_bar_bar1_wait(struct nvkm_bar *base)
+{
+ /* NFI why it's twice. */
+ nvkm_bar_flush(base);
+ nvkm_bar_flush(base);
+}
+
+void
+gf100_bar_bar1_init(struct nvkm_bar *base)
+{
+ struct nvkm_device *device = base->subdev.device;
+ struct gf100_bar *bar = gf100_bar(base);
+ const u32 addr = nvkm_memory_addr(bar->bar[1].mem) >> 12;
+ nvkm_wr32(device, 0x001704, 0x80000000 | addr);
+}
+
void
gf100_bar_init(struct nvkm_bar *base)
{
struct nvkm_device *device = bar->base.subdev.device;
u32 addr;
- addr = nvkm_memory_addr(bar->bar[1].mem) >> 12;
- nvkm_wr32(device, 0x001704, 0x80000000 | addr);
-
if (bar->bar[0].mem) {
addr = nvkm_memory_addr(bar->bar[0].mem) >> 12;
if (bar->bar2_halve)
.dtor = gf100_bar_dtor,
.oneinit = gf100_bar_oneinit,
.init = gf100_bar_init,
+ .bar1.init = gf100_bar_bar1_init,
+ .bar1.wait = gf100_bar_bar1_wait,
.kmap = gf100_bar_kmap,
.umap = gf100_bar_umap,
.flush = g84_bar_flush,
void *gf100_bar_dtor(struct nvkm_bar *);
int gf100_bar_oneinit(struct nvkm_bar *);
void gf100_bar_init(struct nvkm_bar *);
+void gf100_bar_bar1_init(struct nvkm_bar *);
+void gf100_bar_bar1_wait(struct nvkm_bar *);
int gf100_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
#endif
gk20a_bar_func = {
.dtor = gf100_bar_dtor,
.oneinit = gf100_bar_oneinit,
- .init = gf100_bar_init,
+ .bar1.init = gf100_bar_bar1_init,
+ .bar1.wait = gf100_bar_bar1_wait,
.umap = gf100_bar_umap,
.flush = g84_bar_flush,
};
spin_unlock_irqrestore(&bar->base.lock, flags);
}
+void
+nv50_bar_bar1_wait(struct nvkm_bar *base)
+{
+ nvkm_bar_flush(base);
+}
+
+void
+nv50_bar_bar1_init(struct nvkm_bar *base)
+{
+ struct nvkm_device *device = base->subdev.device;
+ struct nv50_bar *bar = nv50_bar(base);
+ nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
+}
+
void
nv50_bar_init(struct nvkm_bar *base)
{
nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12);
nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12);
- nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4);
nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar2->node->offset >> 4);
for (i = 0; i < 8; i++)
nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000);
.dtor = nv50_bar_dtor,
.oneinit = nv50_bar_oneinit,
.init = nv50_bar_init,
+ .bar1.init = nv50_bar_bar1_init,
+ .bar1.wait = nv50_bar_bar1_wait,
.kmap = nv50_bar_kmap,
.umap = nv50_bar_umap,
.flush = nv50_bar_flush,
void *nv50_bar_dtor(struct nvkm_bar *);
int nv50_bar_oneinit(struct nvkm_bar *);
void nv50_bar_init(struct nvkm_bar *);
+void nv50_bar_bar1_init(struct nvkm_bar *);
+void nv50_bar_bar1_wait(struct nvkm_bar *);
struct nvkm_vm *nv50_bar_kmap(struct nvkm_bar *);
int nv50_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
void nv50_bar_unmap(struct nvkm_bar *, struct nvkm_vma *);
void *(*dtor)(struct nvkm_bar *);
int (*oneinit)(struct nvkm_bar *);
void (*init)(struct nvkm_bar *);
+
+ struct {
+ void (*init)(struct nvkm_bar *);
+ void (*wait)(struct nvkm_bar *);
+ } bar1;
+
struct nvkm_vm *(*kmap)(struct nvkm_bar *);
int (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
void (*flush)(struct nvkm_bar *);