dt-bindings: drm/msm/a6xx: Document GMU and update GPU bindings

Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index f8759145ce1a08e57046f4aa63198e642887b4e8..aad1aef682f7a56933096fa1af638ae3842d8779 100644 (file)
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -10,14 +10,23 @@ Required properties:
   If "amd,imageon" is used, there should be no top level msm device.
 - reg: Physical base address and length of the controller's registers.
 - interrupts: The interrupt signal from the gpu.
-- clocks: device clocks
+- clocks: device clocks (if applicable)
   See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required:
+- clock-names: the following clocks are required by a3xx, a4xx and a5xx
+  cores:
   * "core"
   * "iface"
   * "mem_iface"
+  For GMU attached devices the GPU clocks are not used and are not required. The
+  following devices should not list clocks:
+   - qcom,adreno-630.2
+- iommus: optional phandle to an adreno iommu instance
+- operating-points-v2: optional phandle to the OPP operating points
+- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
+  control the power for the GPU. Applicable targets:
+    - qcom,adreno-630.2
 
-Example:
+Example 3xx/4xx/a5xx:
 
 / {
        ...
@@ -37,3 +46,30 @@ Example:
                    <&mmcc MMSS_IMEM_AHB_CLK>;
        };
 };
+
+Example a6xx (with GMU):
+
+/ {
+       ...
+
+       gpu@5000000 {
+               compatible = "qcom,adreno-630.2", "qcom,adreno";
+               #stream-id-cells = <16>;
+
+               reg = <0x5000000 0x40000>, <0x509e000 0x10>;
+               reg-names = "kgsl_3d0_reg_memory", "cx_mem";
+
+               /*
+                * Look ma, no clocks! The GPU clocks and power are
+                * controlled entirely by the GMU
+                */
+
+               interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+               iommus = <&adreno_smmu 0>;
+
+               operating-points-v2 = <&gpu_opp_table>;
+
+               qcom,gmu = <&gmu>;
+       };
+};