drm/mediatek: add dphy reset after setting lanes number

Add dphy reset after setting lanes number to avoid dphy fifo effor.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 989e55f3e0c06269e09df610262a1f88c09d8d8f..c62b9b496036b092e678fa267e6d056fc9068963 100644 (file)
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -39,6 +39,7 @@
 #define DSI_CON_CTRL           0x10
 #define DSI_RESET                      BIT(0)
 #define DSI_EN                         BIT(1)
+#define DPHY_RESET                     BIT(2)
 
 #define DSI_MODE_CTRL          0x14
 #define MODE                           (3)
@@ -282,6 +283,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
        mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 }
 
+static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
+{
+       mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
+       mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
+}
+
 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 {
        mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -652,6 +659,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
        mtk_dsi_phy_timconfig(dsi);
 
        mtk_dsi_rxtx_control(dsi);
+       usleep_range(30, 100);
+       mtk_dsi_reset_dphy(dsi);
        mtk_dsi_ps_control_vact(dsi);
        mtk_dsi_set_vm_cmd(dsi);
        mtk_dsi_config_vdo_timing(dsi);