arm64: dts: marvell: Add AP806-quad cache description

Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index c25bc65727b5436be752af9d891f84843aab6395..3db427122f9e7650132596d5580ec16add691535 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -22,6 +22,13 @@ cpu0: cpu@0 {
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 0>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_0>;
                };
                cpu1: cpu@1 {
                        device_type = "cpu";
@@ -30,6 +37,13 @@ cpu1: cpu@1 {
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 0>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_0>;
                };
                cpu2: cpu@100 {
                        device_type = "cpu";
@@ -38,6 +52,13 @@ cpu2: cpu@100 {
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 1>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
                };
                cpu3: cpu@101 {
                        device_type = "cpu";
@@ -46,6 +67,27 @@ cpu3: cpu@101 {
                        enable-method = "psci";
                        #cooling-cells = <2>;
                        clocks = <&cpu_clk 1>;
+                       i-cache-size = <0xc000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <256>;
+                       next-level-cache = <&l2_1>;
+               };
+
+               l2_0: l2-cache0 {
+                       compatible = "cache";
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+               };
+
+               l2_1: l2-cache1 {
+                       compatible = "cache";
+                       cache-size = <0x80000>;
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
                };
        };
 };