staging: mt7621-pci-phy: remove disable clock from the phy exit function

The clock which has been used here is not about the phy but the pcie port.
It has been properly handled into host pcie driver code. Hence, remove it
from here which is the correct thing to do.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
index 2576f179e30afe274c78d1ea458a7f1145ae1f99..d2a07f145143af1a2abe96cedc4fd0754122885f 100644 (file)
--- a/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
+++ b/drivers/staging/mt7621-pci-phy/pci-mt7621-phy.c
@@ -16,10 +16,6 @@
 #include <mt7621.h>
 #include <ralink_regs.h>
 
-#define RALINK_CLKCFG1                         0x30
-
-#define PCIE_PORT_CLK_EN(x)                    BIT(24 + (x))
-
 #define RG_PE1_PIPE_REG                                0x02c
 #define RG_PE1_PIPE_RST                                BIT(12)
 #define RG_PE1_PIPE_CMD_FRC                    BIT(4)
@@ -286,10 +282,6 @@ static int mt7621_pci_phy_power_off(struct phy *phy)
 
 static int mt7621_pci_phy_exit(struct phy *phy)
 {
-       struct mt7621_pci_phy_instance *instance = phy_get_drvdata(phy);
-
-       rt_sysc_m32(PCIE_PORT_CLK_EN(instance->index), 0, RALINK_CLKCFG1);
-
        return 0;
 }