drm/nouveau/mmu/nv41: implement vmm on top of new base

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
index 64684a7440001a47e7e3a4cabb2730de34e2afe7..4b3e403a76f34e6095494e21b371572e3b1387c4 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
@@ -14,3 +14,4 @@ nvkm-y += nvkm/subdev/mmu/gp10b.o
 
 nvkm-y += nvkm/subdev/mmu/vmm.o
 nvkm-y += nvkm/subdev/mmu/vmmnv04.o
+nvkm-y += nvkm/subdev/mmu/vmmnv41.o

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
index 9b5375c587a7f5e9d5c2270a0cf8af67b8aa6672..cb037f4a1780b69464e4934f4158a416ebe3f40d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
@@ -21,12 +21,13 @@
  *
  * Authors: Ben Skeggs
  */
-#include "nv04.h"
+#include "vmm.h"
 
-#include <core/gpuobj.h>
 #include <core/option.h>
 #include <subdev/timer.h>
 
+#include <nvif/class.h>
+
 #define NV41_GART_SIZE (512 * 1024 * 1024)
 #define NV41_GART_PAGE (  4 * 1024)
 
@@ -68,17 +69,17 @@ nv41_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)
 static void
 nv41_vm_flush(struct nvkm_vm *vm)
 {
-       struct nv04_mmu *mmu = nv04_mmu(vm->mmu);
-       struct nvkm_device *device = mmu->base.subdev.device;
+       struct nvkm_subdev *subdev = &vm->mmu->subdev;
+       struct nvkm_device *device = subdev->device;
 
-       mutex_lock(&mmu->base.subdev.mutex);
+       mutex_lock(&subdev->mutex);
        nvkm_wr32(device, 0x100810, 0x00000022);
        nvkm_msec(device, 2000,
                if (nvkm_rd32(device, 0x100810) & 0x00000020)
                        break;
        );
        nvkm_wr32(device, 0x100810, 0x00000000);
-       mutex_unlock(&mmu->base.subdev.mutex);
+       mutex_unlock(&subdev->mutex);
 }
 
 /*******************************************************************************
@@ -86,38 +87,24 @@ nv41_vm_flush(struct nvkm_vm *vm)
  ******************************************************************************/
 
 static int
-nv41_mmu_oneinit(struct nvkm_mmu *base)
+nv41_mmu_oneinit(struct nvkm_mmu *mmu)
 {
-       struct nv04_mmu *mmu = nv04_mmu(base);
-       struct nvkm_device *device = mmu->base.subdev.device;
-       int ret;
-
-       ret = nvkm_vm_create(&mmu->base, 0, NV41_GART_SIZE, 0, 4096, NULL,
-                            &mmu->base.vmm);
-       if (ret)
-               return ret;
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
-                             (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16, true,
-                             &mmu->base.vmm->pgt[0].mem[0]);
-       mmu->base.vmm->pgt[0].refcount[0] = 1;
-       return ret;
+       mmu->vmm->pgt[0].mem[0] = mmu->vmm->pd->pt[0]->memory;
+       mmu->vmm->pgt[0].refcount[0] = 1;
+       return 0;
 }
 
 static void
-nv41_mmu_init(struct nvkm_mmu *base)
+nv41_mmu_init(struct nvkm_mmu *mmu)
 {
-       struct nv04_mmu *mmu = nv04_mmu(base);
-       struct nvkm_device *device = mmu->base.subdev.device;
-       struct nvkm_memory *dma = mmu->base.vmm->pgt[0].mem[0];
-       nvkm_wr32(device, 0x100800, 0x00000002 | nvkm_memory_addr(dma));
+       struct nvkm_device *device = mmu->subdev.device;
+       nvkm_wr32(device, 0x100800, 0x00000002 | mmu->vmm->pd->pt[0]->addr);
        nvkm_mask(device, 0x10008c, 0x00000100, 0x00000100);
        nvkm_wr32(device, 0x100820, 0x00000000);
 }
 
 static const struct nvkm_mmu_func
 nv41_mmu = {
-       .dtor = nv04_mmu_dtor,
        .oneinit = nv41_mmu_oneinit,
        .init = nv41_mmu_init,
        .limit = NV41_GART_SIZE,
@@ -128,6 +115,7 @@ nv41_mmu = {
        .map_sg = nv41_vm_map_sg,
        .unmap = nv41_vm_unmap,
        .flush = nv41_vm_flush,
+       .vmm = {{ -1, -1, NVIF_CLASS_VMM_NV04}, nv41_vmm_new, true },
 };
 
 int
@@ -137,5 +125,5 @@ nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)
            !nvkm_boolopt(device->cfgopt, "NvPCIE", true))
                return nv04_mmu_new(device, index, pmmu);
 
-       return nv04_mmu_new_(&nv41_mmu, device, index, pmmu);
+       return nvkm_mmu_new_(&nv41_mmu, device, index, pmmu);
 }

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
index 093ddb497c9306e99b68fb07056a01c2075e2537..16d4a4c7aae4cf5f1b682c3e78093e554d19b8f6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h
@@ -105,6 +105,9 @@ void nvkm_vmm_dtor(struct nvkm_vmm *);
 int nv04_vmm_new_(const struct nvkm_vmm_func *, struct nvkm_mmu *, u32,
                  u64, u64, void *, u32, struct lock_class_key *,
                  const char *, struct nvkm_vmm **);
+
 int nv04_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
                 struct lock_class_key *, const char *, struct nvkm_vmm **);
+int nv41_vmm_new(struct nvkm_mmu *, u64, u64, void *, u32,
+                struct lock_class_key *, const char *, struct nvkm_vmm **);
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c
new file mode 100644 (file)
index 0000000..8a624d7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "vmm.h"
+
+static const struct nvkm_vmm_desc_func
+nv41_vmm_desc_pgt = {
+};
+
+static const struct nvkm_vmm_desc
+nv41_vmm_desc_12[] = {
+       { PGT, 17, 4, 0x1000, &nv41_vmm_desc_pgt },
+       {}
+};
+
+static const struct nvkm_vmm_func
+nv41_vmm = {
+       .page = {
+               { 12, &nv41_vmm_desc_12[0], NVKM_VMM_PAGE_HOST },
+               {}
+       }
+};
+
+int
+nv41_vmm_new(struct nvkm_mmu *mmu, u64 addr, u64 size, void *argv, u32 argc,
+            struct lock_class_key *key, const char *name,
+            struct nvkm_vmm **pvmm)
+{
+       return nv04_vmm_new_(&nv41_vmm, mmu, 0, addr, size,
+                            argv, argc, key, name, pvmm);
+}