drm/amd/display: change bw_dceip and bw_vbios into pointers

-Change bw_calcs_dceip into pointer
-Change bw_calcs_vbios into pointer

This is needed for flattening of core_dc into dc, as without this the
diags build fails

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index aeed95a5d0978cba68077e42e80a400885fc4fb7..477024c467e63292e07c4effdcf42a3a596f34a9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -433,6 +433,13 @@ static void destruct(struct core_dc *dc)
 
        dm_free(dc->ctx);
        dc->ctx = NULL;
+
+       dm_free(dc->bw_vbios);
+       dc->bw_vbios = NULL;
+
+       dm_free(dc->bw_dceip);
+       dc->bw_dceip = NULL;
+
 }
 
 static bool construct(struct core_dc *dc,
@@ -440,8 +447,25 @@ static bool construct(struct core_dc *dc,
 {
        struct dal_logger *logger;
        struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
+       struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip));
+       struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios));
+
        enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 
+       if (!dc_dceip) {
+               dm_error("%s: failed to create dceip\n", __func__);
+               goto dceip_fail;
+       }
+
+       dc->bw_dceip = dc_dceip;
+
+       if (!dc_vbios) {
+               dm_error("%s: failed to create vbios\n", __func__);
+               goto vbios_fail;
+       }
+
+       dc->bw_vbios = dc_vbios;
+
        if (!dc_ctx) {
                dm_error("%s: failed to create ctx\n", __func__);
                goto ctx_fail;
@@ -544,6 +568,8 @@ static bool construct(struct core_dc *dc,
 logger_fail:
 val_ctx_fail:
 ctx_fail:
+dceip_fail:
+vbios_fail:
        destruct(dc);
        return false;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 5b46e776b9b7b6987d4efbf7cdaf59c37c657b6a..ccde7c80d6581970ec24a2a96c93cde65f3ef6e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1264,7 +1264,7 @@ void dce110_set_displaymarks(
                        continue;
 
                total_dest_line_time_ns = compute_pstate_blackout_duration(
-                       dc->bw_vbios.blackout_duration, pipe_ctx->stream);
+                       dc->bw_vbios->blackout_duration, pipe_ctx->stream);
                pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
                        pipe_ctx->plane_res.mi,
                        context->bw.dce.nbp_state_change_wm_ns[num_pipes],

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index a7f30dcc906c81f52a0b695f795ebc33849fcd68..56be84ce5a0d3fe871a09d6ba8af44b199971eb4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -826,8 +826,8 @@ static bool dce110_validate_bandwidth(
 
        if (bw_calcs(
                        dc->ctx,
-                       &dc->bw_dceip,
-                       &dc->bw_vbios,
+                       dc->bw_dceip,
+                       dc->bw_vbios,
                        context->res_ctx.pipe_ctx,
                        dc->res_pool->pipe_count,
                        &context->bw.dce))
@@ -1127,21 +1127,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
                        DM_PP_CLOCK_TYPE_ENGINE_CLK,
                        &clks);
        /* convert all the clock fro kHz to fix point mHz */
-       dc->bw_vbios.high_sclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_sclk = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels-1], 1000);
-       dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels/8], 1000);
-       dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels*2/8], 1000);
-       dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels*3/8], 1000);
-       dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels*4/8], 1000);
-       dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels*5/8], 1000);
-       dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels*6/8], 1000);
-       dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[0], 1000);
        dc->sclk_lvls = clks;
 
@@ -1150,11 +1150,11 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
                        dc->ctx,
                        DM_PP_CLOCK_TYPE_DISPLAY_CLK,
                        &clks);
-       dc->bw_vbios.high_voltage_max_dispclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels-1], 1000);
-       dc->bw_vbios.mid_voltage_max_dispclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid_voltage_max_dispclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels>>1], 1000);
-       dc->bw_vbios.low_voltage_max_dispclk  = bw_frc_to_fixed(
+       dc->bw_vbios->low_voltage_max_dispclk  = bw_frc_to_fixed(
                        clks.clocks_in_khz[0], 1000);
 
        /*do memory clock*/
@@ -1163,12 +1163,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
                        DM_PP_CLOCK_TYPE_MEMORY_CLK,
                        &clks);
 
-       dc->bw_vbios.low_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->low_yclk = bw_frc_to_fixed(
                clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-       dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
                clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
                1000);
-       dc->bw_vbios.high_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_yclk = bw_frc_to_fixed(
                clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
                1000);
 }
@@ -1353,7 +1353,7 @@ static bool construct(
 
        dc->public.caps.max_planes =  pool->base.pipe_count;
 
-       bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
+       bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 
        bw_calcs_data_update_from_pplib(dc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 420434d7283edb9d9f0aa1688c6d2935ef15ea9b..d6e58a25f3d0472aa68fddacfd112adafef1c4a7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -771,8 +771,8 @@ bool dce112_validate_bandwidth(
 
        if (bw_calcs(
                        dc->ctx,
-                       &dc->bw_dceip,
-                       &dc->bw_vbios,
+                       dc->bw_dceip,
+                       dc->bw_vbios,
                        context->res_ctx.pipe_ctx,
                        dc->res_pool->pipe_count,
                        &context->bw.dce))
@@ -1018,21 +1018,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
                                DM_PP_CLOCK_TYPE_ENGINE_CLK,
                                &clks);
                /* convert all the clock fro kHz to fix point mHz */
-               dc->bw_vbios.high_sclk = bw_frc_to_fixed(
+               dc->bw_vbios->high_sclk = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels-1], 1000);
-               dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels/8], 1000);
-               dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels*2/8], 1000);
-               dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels*3/8], 1000);
-               dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels*4/8], 1000);
-               dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels*5/8], 1000);
-               dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[clks.num_levels*6/8], 1000);
-               dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
+               dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
                                clks.clocks_in_khz[0], 1000);
 
                /*do memory clock*/
@@ -1041,12 +1041,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
                                DM_PP_CLOCK_TYPE_MEMORY_CLK,
                                &clks);
 
-               dc->bw_vbios.low_yclk = bw_frc_to_fixed(
+               dc->bw_vbios->low_yclk = bw_frc_to_fixed(
                        clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
-               dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
+               dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
                        1000);
-               dc->bw_vbios.high_yclk = bw_frc_to_fixed(
+               dc->bw_vbios->high_yclk = bw_frc_to_fixed(
                        clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
                        1000);
 
@@ -1054,21 +1054,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
        }
 
        /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
-       dc->bw_vbios.high_sclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_sclk = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
-       dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
-       dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
                        eng_clks.data[0].clocks_in_khz, 1000);
 
        /*do memory clock*/
@@ -1082,12 +1082,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
         * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
         * YCLK = UMACLK*m_memoryTypeMultiplier
         */
-       dc->bw_vbios.low_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->low_yclk = bw_frc_to_fixed(
                mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
-       dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
                mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
                1000);
-       dc->bw_vbios.high_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_yclk = bw_frc_to_fixed(
                mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
                1000);
 
@@ -1325,7 +1325,7 @@ static bool construct(
        if (!dce112_hw_sequencer_construct(dc))
                goto res_create_fail;
 
-       bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
+       bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 
        bw_calcs_data_update_from_pplib(dc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index d4e962756fbb737073a525e213eecca1197f2036..562ae2205a905627fccf352dd41fae1cb9d7f07a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -729,21 +729,21 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
        }
 
        /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
-       dc->bw_vbios.high_sclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_sclk = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
-       dc->bw_vbios.mid1_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid2_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid3_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid4_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid5_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
-       dc->bw_vbios.mid6_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
                eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
-       dc->bw_vbios.low_sclk  = bw_frc_to_fixed(
+       dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
                        eng_clks.data[0].clocks_in_khz, 1000);
 
        /*do memory clock*/
@@ -770,12 +770,12 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
         * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
         * YCLK = UMACLK*m_memoryTypeMultiplier
         */
-       dc->bw_vbios.low_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->low_yclk = bw_frc_to_fixed(
                mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
-       dc->bw_vbios.mid_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
                mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
                1000);
-       dc->bw_vbios.high_yclk = bw_frc_to_fixed(
+       dc->bw_vbios->high_yclk = bw_frc_to_fixed(
                mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
                1000);
 
@@ -984,7 +984,7 @@ static bool construct(
 
        dc->public.caps.max_planes =  pool->base.pipe_count;
 
-       bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
+       bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
 
        bw_calcs_data_update_from_pplib(dc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index 1ecb54603e170cfeba512f43b1ef5b36b13f7ca3..982f7170f5d23c0b6609244edd72b62db33af111 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -29,8 +29,8 @@ struct core_dc {
        struct dm_pp_clock_levels sclk_lvls;
 
        /* Inputs into BW and WM calculations. */
-       struct bw_calcs_dceip bw_dceip;
-       struct bw_calcs_vbios bw_vbios;
+       struct bw_calcs_dceip *bw_dceip;
+       struct bw_calcs_vbios *bw_vbios;
 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
        struct dcn_soc_bounding_box dcn_soc;
        struct dcn_ip_params dcn_ip;