perf/x86/intel/uncore: Enable EV_SEL_EXT bit for PCU

This patch adds support for the SNB-EP PCU uncore PMU extra_sel_bit
(bit 21) which is missing from the documentation in Table-2.75 of
Intel Xeon Processor E5-2600 Product Family Uncore Performance
Monitoring Guide. It is referred to later in Table-2.81. Without
this selection bit explicitly enabled by the kernel, some events
such as COREx_TRANSITION_CYCLES do not count correctly.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Reviewed-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1376375382-21350-4-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 6b8b9c951aad6bef485d77d803f1ab2699cdd8ea..e9696d8269ba957511273cae26415c0a05bb8e3d 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -301,7 +301,7 @@ static struct attribute *snbep_uncore_cbox_formats_attr[] = {
 };
 
 static struct attribute *snbep_uncore_pcu_formats_attr[] = {
-       &format_attr_event.attr,
+       &format_attr_event_ext.attr,
        &format_attr_occ_sel.attr,
        &format_attr_edge.attr,
        &format_attr_inv.attr,

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 628500e65d0b51fe0030a6b548cefb88ea320f8d..a80ab71a883de06be3cbed3a8c0848aa1dfff69a 100644 (file)
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -117,6 +117,7 @@
                                (SNBEP_PMON_CTL_EV_SEL_MASK | \
                                 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
                                 SNBEP_PMON_CTL_EDGE_DET | \
+                                SNBEP_PMON_CTL_EV_SEL_EXT | \
                                 SNBEP_PMON_CTL_INVERT | \
                                 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
                                 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \