]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
sh_eth: fix *enum* {A|M}PR_BIT
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tue, 26 Jun 2018 15:42:33 +0000 (18:42 +0300)
committerDavid S. Miller <davem@davemloft.net>
Thu, 28 Jun 2018 07:02:04 +0000 (16:02 +0900)
The *enum* {A|M}PR_BIT were declared in the commit 86a74ff21a7a ("net:
sh_eth: add support for  Renesas SuperH Ethernet") adding SH771x support,
however the SH771x manual  doesn't have the APR/MPR registers described
and the code writing to them for SH7710 was later removed by the commit
380af9e390ec ("net: sh_eth: CPU dependency code collect to "struct
sh_eth_cpu_data""). All the newer SoC manuals have these registers
documented as having a 16-bit TIME parameter of the PAUSE frame, not
1-bit -- update the *enum* accordingly, fixing up the APR/MPR writes...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/renesas/sh_eth.c
drivers/net/ethernet/renesas/sh_eth.h

index f7043ea5eed13098bbf4a851c63b05b2405b7a5b..71651e47660a256ee901e5286475b8ea3d817af0 100644 (file)
@@ -1521,9 +1521,9 @@ static int sh_eth_dev_init(struct net_device *ndev)
 
        /* mask reset */
        if (mdp->cd->apr)
-               sh_eth_write(ndev, APR_AP, APR);
+               sh_eth_write(ndev, 1, APR);
        if (mdp->cd->mpr)
-               sh_eth_write(ndev, MPR_MP, MPR);
+               sh_eth_write(ndev, 1, MPR);
        if (mdp->cd->tpauser)
                sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
 
index a03d99f51ccfc89303124e1d0815d3762332f077..140ad2c570950c65c016aa491a89ce4056b87188 100644 (file)
@@ -383,12 +383,12 @@ enum ECSIPR_STATUS_MASK_BIT {
 
 /* APR */
 enum APR_BIT {
-       APR_AP = 0x00000001,
+       APR_AP = 0x0000ffff,
 };
 
 /* MPR */
 enum MPR_BIT {
-       MPR_MP = 0x00000001,
+       MPR_MP = 0x0000ffff,
 };
 
 /* TRSCER */