]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/dp: Add helper to get post-cursor adjustments
authorThierry Reding <treding@nvidia.com>
Mon, 21 Oct 2019 14:34:31 +0000 (16:34 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 23 Oct 2019 16:18:48 +0000 (18:18 +0200)
If the transmitter supports pre-emphasis post cursor2 the sink will
request adjustments in a similar way to how it requests adjustments to
the voltage swing and pre-emphasis settings.

Add a helper to extract these adjustments on a per-lane basis from the
DPCD link status.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021143437.1477719-8-thierry.reding@gmail.com
drivers/gpu/drm/drm_dp_helper.c
include/drm/drm_dp_helper.h

index ac802b04f12093f57f570b3c1f66c029e0910ebf..f567141aff54ba50c17860d42c4344ddea33c0fa 100644 (file)
@@ -120,6 +120,16 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 }
 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 
+u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
+                                        unsigned int lane)
+{
+       unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
+       u8 value = dp_link_status(link_status, offset);
+
+       return (value >> (lane << 1)) & 0x3;
+}
+EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
+
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
        unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
index b3402cb186a47f2c27a68e5ece5c3a9562c74028..04f6c0bb02747abc7547df430c54980e57397350 100644 (file)
 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
 
 #define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
+# define DP_ADJUST_POST_CURSOR2_LANE0_MASK  0x03
+# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
+# define DP_ADJUST_POST_CURSOR2_LANE1_MASK  0x0c
+# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
+# define DP_ADJUST_POST_CURSOR2_LANE2_MASK  0x30
+# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
+# define DP_ADJUST_POST_CURSOR2_LANE3_MASK  0xc0
+# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
 
 #define DP_TEST_REQUEST                            0x218
 # define DP_TEST_LINK_TRAINING             (1 << 0)
@@ -1122,6 +1130,8 @@ u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
                                     int lane);
 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
                                          int lane);
+u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
+                                        unsigned int lane);
 
 #define DP_BRANCH_OUI_HEADER_SIZE      0xc
 #define DP_RECEIVER_CAP_SIZE           0xf