]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: vf610-zii-dev-rev-b: add PHYs for switch2
authorRussell King <rmk+kernel@armlinux.org.uk>
Wed, 20 Dec 2017 23:11:55 +0000 (23:11 +0000)
committerShawn Guo <shawnguo@kernel.org>
Tue, 26 Dec 2017 08:47:10 +0000 (16:47 +0800)
Switch 2 has an 88e1545 PHY behind it, which is a quad PHY.  Only the
first three PHYs are used, the remaining PHY is unused.  When we wire
up the SFF sockets in a later commit, the omission of this causes the
fourth PHY to be used for port 3.  Specifying the PHYs in DT avoids
the auto-probing of the bus, and discovery of this PHY.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts

index ede8649ba51527c7091c6d5909b4a561c9678229..782b69a3acdfaef71b3e035a79c3da1e707c8c20 100644 (file)
@@ -255,16 +255,19 @@ ports {
                                        port@0 {
                                                reg = <0>;
                                                label = "lan6";
+                                               phy-handle = <&switch2phy0>;
                                        };
 
                                        port@1 {
                                                reg = <1>;
                                                label = "lan7";
+                                               phy-handle = <&switch2phy1>;
                                        };
 
                                        port@2 {
                                                reg = <2>;
                                                label = "lan8";
+                                               phy-handle = <&switch2phy2>;
                                        };
 
                                        port@3 {
@@ -304,6 +307,20 @@ fixed-link {
                                                };
                                        };
                                };
+                               mdio {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       switch2phy0: phy@0 {
+                                               reg = <0>;
+                                       };
+                                       switch2phy1: phy@1 {
+                                               reg = <1>;
+                                       };
+                                       switch2phy2: phy@2 {
+                                               reg = <2>;
+                                       };
+                               };
                        };
                };