]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/bridge: analogix_dp: Properly disable aux chan retries on rockchip
authorDouglas Anderson <dianders@chromium.org>
Mon, 23 Apr 2018 10:49:56 +0000 (12:49 +0200)
committerAndrzej Hajda <a.hajda@samsung.com>
Tue, 24 Apr 2018 06:34:46 +0000 (08:34 +0200)
The comments in analogix_dp_init_aux() claim that we're disabling aux
channel retries, but then right below it for Rockchip it sets them to
3.  If we actually need 3 retries for Rockchip then we could adjust
the comment, but it seems more likely that we want the same retry
behavior across all platforms.

Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: 征增 王 <wzz@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-21-enric.balletbo@collabora.com
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

index 58e8a28e99aa40cc3c53acfb436e96ce65fc3d37..a5f2763d72e4b404eda77374e88da61806840474 100644 (file)
@@ -481,15 +481,16 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 
        analogix_dp_reset_aux(dp);
 
-       /* Disable AUX transaction H/W retry */
+       /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
        if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
-               reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
-                     AUX_HW_RETRY_COUNT_SEL(3) |
-                     AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+               reg = 0;
        else
-               reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
-                     AUX_HW_RETRY_COUNT_SEL(0) |
-                     AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+               reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
+
+       /* Disable AUX transaction H/W retry */
+       reg |= AUX_HW_RETRY_COUNT_SEL(0) |
+              AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+
        writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
        /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */