drm/i915: Disable display interrupts during display IRQ handler

During the Display Interrupt Service routine the Display Interrupt
Enable bit must be disabled, The interrupts handled, then the
Display Interrupt Enable bit must be set to prevent possible missed
interrupts.

Bspec: 49212
V2: Change Title to remove SDE reference.
V3: Fix TAB spacing.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191121201455.2558-1-clinton.a.taylor@intel.com

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dae00f7dd7df83d6c387c576b2ff2c077fb2a02b..8b338744eddfddba7cc47841b60fd956c8cefd1d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2484,7 +2484,11 @@ __gen11_irq_handler(struct drm_i915_private * const i915,
                 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
                 * for the display related bits.
                 */
+               raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
                gen8_de_irq_handler(i915, disp_ctl);
+               raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
+                             GEN11_DISPLAY_IRQ_ENABLE);
+
                enable_rpm_wakeref_asserts(&i915->runtime_pm);
        }