ARM: dts: exynos: Use labels instead of full paths in exynos4210-universal_c210

Extend camera, fimc, mct and sysram nodes by labels, not by full path in
Exynos 4210 Universal C210 board.  This avoids error-prone redefinition
of nodes.

Signed-off-by: Maciej Purski <m.purski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 21fff7cd3aa49b08302298ed3a7e59fc0b9e8d27..4e6ff97e1ec41840aed2c4705ee1041c1c50aed1 100644 (file)
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,24 +28,6 @@ chosen {
                stdout-path = &serial_2;
        };
 
-       sysram@2020000 {
-               smp-sysram@0 {
-                       status = "disabled";
-               };
-
-               smp-sysram@5000 {
-                       compatible = "samsung,exynos4210-sysram";
-                       reg = <0x5000 0x1000>;
-               };
-
-               smp-sysram@1f000 {
-                       status = "disabled";
-               };
-       };
-
-       mct@10050000 {
-               compatible = "none";
-       };
 
        fixed-rate-clocks {
                xxti {
@@ -173,45 +155,6 @@ lcd_ep: endpoint {
                };
        };
 
-       camera {
-               status = "okay";
-
-               pinctrl-names = "default";
-               pinctrl-0 = <>;
-
-               fimc_0: fimc@11800000 {
-                       status = "okay";
-                       assigned-clocks = <&clock CLK_MOUT_FIMC0>,
-                                       <&clock CLK_SCLK_FIMC0>;
-                       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                       assigned-clock-rates = <0>, <160000000>;
-               };
-
-               fimc_1: fimc@11810000 {
-                       status = "okay";
-                       assigned-clocks = <&clock CLK_MOUT_FIMC1>,
-                                       <&clock CLK_SCLK_FIMC1>;
-                       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                       assigned-clock-rates = <0>, <160000000>;
-               };
-
-               fimc_2: fimc@11820000 {
-                       status = "okay";
-                       assigned-clocks = <&clock CLK_MOUT_FIMC2>,
-                                       <&clock CLK_SCLK_FIMC2>;
-                       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                       assigned-clock-rates = <0>, <160000000>;
-               };
-
-               fimc_3: fimc@11830000 {
-                       status = "okay";
-                       assigned-clocks = <&clock CLK_MOUT_FIMC3>,
-                                       <&clock CLK_SCLK_FIMC3>;
-                       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                       assigned-clock-rates = <0>, <160000000>;
-               };
-       };
-
        hdmi_en: voltage-regulator-hdmi-5v {
                compatible = "regulator-fixed";
                regulator-name = "HDMI_5V";
@@ -234,6 +177,13 @@ hdmi_ddc: i2c-ddc {
        };
 };
 
+&camera {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <>;
+};
+
 &cpu0 {
        cpu0-supply = <&vdd_arm_reg>;
 };
@@ -250,6 +200,38 @@ &exynos_usbphy {
        vbus-supply = <&safeout1_reg>;
 };
 
+&fimc_0 {
+       status = "okay";
+       assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                         <&clock CLK_SCLK_FIMC0>;
+       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+       assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+       status = "okay";
+       assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                         <&clock CLK_SCLK_FIMC1>;
+       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+       assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+       status = "okay";
+       assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                         <&clock CLK_SCLK_FIMC2>;
+       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+       assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+       status = "okay";
+       assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                         <&clock CLK_SCLK_FIMC3>;
+       assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+       assigned-clock-rates = <0>, <160000000>;
+};
+
 &fimd {
        pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
        pinctrl-names = "default";
@@ -501,6 +483,10 @@ &i2c_8 {
        status = "okay";
 };
 
+&mct {
+       compatible = "none";
+};
+
 &mdma1 {
        reg = <0x12840000 0x1000>;
 };
@@ -579,3 +565,18 @@ &serial_3 {
        /delete-property/dmas;
        /delete-property/dma-names;
 };
+
+&sysram {
+       smp-sysram@0 {
+               status = "disabled";
+       };
+
+       smp-sysram@5000 {
+               compatible = "samsung,exynos4210-sysram";
+               reg = <0x5000 0x1000>;
+       };
+
+       smp-sysram@1f000 {
+               status = "disabled";
+       };
+};