drm/amd/display: Fix underscan not using proper scaling

fix underscan not being set correctly

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4df5bf750257a43002dc06f42cfefa160f64b5a6..12aeb6d83f42aecc0748d7ac15bc5594471a2bc2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1362,7 +1362,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
        enum surface_update_type update_type;
        struct dc_state *context;
        struct dc_context *dc_ctx = dc->ctx;
-       int i;
+       int i, j;
 
        stream_status = dc_stream_get_status(stream);
        context = dc->current_state;
@@ -1396,8 +1396,17 @@ void dc_commit_updates_for_stream(struct dc *dc,
                if (srf_updates[i].flip_addr)
                        surface->address = srf_updates[i].flip_addr->address;
 
-       }
+               if (update_type >= UPDATE_TYPE_MED) {
+                       for (j = 0; j < dc->res_pool->pipe_count; j++) {
+                               struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
+
+                               if (pipe_ctx->plane_state != surface)
+                                       continue;
 
+                               resource_build_scaling_params(pipe_ctx);
+                       }
+               }
+       }
 
        commit_planes_for_stream(
                                dc,