]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: update interrupt callback for all ras clients
authorTao Zhou <tao.zhou1@amd.com>
Mon, 22 Jul 2019 12:33:39 +0000 (20:33 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 31 Jul 2019 19:50:29 +0000 (14:50 -0500)
add err_data parameter in interrupt cb for ras clients

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

index 65be73eb02d4b2a0f67095c9302b5c7fadb3f38a..8e8d92b1a04748fceed1fa9e5c1679642eee446e 100644 (file)
@@ -3955,6 +3955,7 @@ static int gfx_v9_0_early_init(void *handle)
 }
 
 static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry);
 
 static int gfx_v9_0_ecc_late_init(void *handle)
@@ -5269,6 +5270,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
 }
 
 static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry)
 {
        /* TODO ue will trigger an interrupt. */
index ae685998b2827bee5d885e2f0191d491fdb2f2e6..06fca08b6513e0d19c3b3c6d75cc79215def1de6 100644 (file)
@@ -243,12 +243,12 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 }
 
 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry)
 {
-       struct ras_err_data err_data = {0, 0};
        kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
        if (adev->umc.funcs->query_ras_error_count)
-               adev->umc.funcs->query_ras_error_count(adev, &err_data);
+               adev->umc.funcs->query_ras_error_count(adev, err_data);
        amdgpu_ras_reset_gpu(adev, 0);
        return AMDGPU_RAS_UE;
 }
index a33bd867287ec0c208c6bc5acd3951f281a43c22..dda0b8d005f86a74a6c32574817f8a05e2beaa18 100644 (file)
@@ -1627,6 +1627,7 @@ static int sdma_v4_0_early_init(void *handle)
 }
 
 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry);
 
 static int sdma_v4_0_late_init(void *handle)
@@ -1960,6 +1961,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
 }
 
 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+               struct ras_err_data *err_data,
                struct amdgpu_iv_entry *entry)
 {
        uint32_t instance, err_source;