drm/i915/color: Extract icl_read_luts()

For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.

This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.

Major change done-removal of readouts of coarse and fine segments
because PAL_PREC_DATA register isn't giving propoer values.
State checker limited only to "fine segment"

v2: -readout code for multisegmented gamma has to come
     up with some intermediate entries that aren't preserved
     in hardware (Jani N)
    -linear interpolation (Ville)
    -moved common code to check gamma_enable to specific funcs,
     since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
    -used single lut [Jani N]
    -improved and more readable for loops [Jani N]
    -read values directly to actual locations and then fill gaps [Jani N]
    -moved cleaning to patch 1 [Jani N]
    -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
     make it similar to icl_load_luts()
    -renamed icl_compute_interpolated_gamma_blob() to
     icl_compute_interpolated_gamma_lut_values() more sensible, I guess
v4: -removed interpolated func for creating gamma lut values
    -removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA
     correctly

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1569096654-24433-3-git-send-email-swati2.sharma@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 91435ba426d015aa38fe529475a92a7018663764..b0268a9bde8a7ddee67f902859308298bf589ea6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1402,6 +1402,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
 
 static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+       if (!crtc_state->gamma_enable)
+               return 0;
+
        switch (crtc_state->gamma_mode) {
        case GAMMA_MODE_MODE_8BIT:
                return 8;
@@ -1415,6 +1418,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+       if (!crtc_state->gamma_enable)
+               return 0;
+
        if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
                return 0;
 
@@ -1431,6 +1437,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+       if (!crtc_state->gamma_enable)
+               return 0;
+
        if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
                return 10;
        else
@@ -1439,6 +1448,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
 
 static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
 {
+       if (!crtc_state->gamma_enable)
+               return 0;
+
        switch (crtc_state->gamma_mode) {
        case GAMMA_MODE_MODE_8BIT:
                return 8;
@@ -1450,21 +1462,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
        }
 }
 
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+       if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+               return 0;
+
+       switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+       case GAMMA_MODE_MODE_8BIT:
+               return 8;
+       case GAMMA_MODE_MODE_10BIT:
+               return 10;
+       case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+               return 16;
+       default:
+               MISSING_CASE(crtc_state->gamma_mode);
+               return 0;
+       }
+
+}
+
 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-       if (!crtc_state->gamma_enable)
-               return 0;
-
        if (HAS_GMCH(dev_priv)) {
                if (IS_CHERRYVIEW(dev_priv))
                        return chv_gamma_precision(crtc_state);
                else
                        return i9xx_gamma_precision(crtc_state);
        } else {
-               if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+               if (INTEL_GEN(dev_priv) >= 11)
+                       return icl_gamma_precision(crtc_state);
+               else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
                        return glk_gamma_precision(crtc_state);
                else if (IS_IRONLAKE(dev_priv))
                        return ilk_gamma_precision(crtc_state);
@@ -1495,6 +1525,20 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
        return true;
 }
 
+static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
+                                             struct drm_color_lut *lut2,
+                                             int lut_size, u32 err)
+{
+       int i;
+
+       for (i = 0; i < 9; i++) {
+               if (!err_check(&lut1[i], &lut2[i], err))
+                       return false;
+       }
+
+       return true;
+}
+
 bool intel_color_lut_equal(struct drm_property_blob *blob1,
                           struct drm_property_blob *blob2,
                           u32 gamma_mode, u32 bit_precision)
@@ -1513,16 +1557,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
        lut_size2 = drm_color_lut_size(blob2);
 
        /* check sw and hw lut size */
-       switch (gamma_mode) {
-       case GAMMA_MODE_MODE_8BIT:
-       case GAMMA_MODE_MODE_10BIT:
-               if (lut_size1 != lut_size2)
-                       return false;
-               break;
-       default:
-               MISSING_CASE(gamma_mode);
-                       return false;
-       }
+       if (lut_size1 != lut_size2)
+               return false;
 
        lut1 = blob1->data;
        lut2 = blob2->data;
@@ -1530,13 +1566,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
        err = 0xffff >> bit_precision;
 
        /* check sw and hw lut entry to be equal */
-       switch (gamma_mode) {
+       switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
        case GAMMA_MODE_MODE_8BIT:
        case GAMMA_MODE_MODE_10BIT:
                if (!intel_color_lut_entry_equal(lut1, lut2,
                                                 lut_size2, err))
                        return false;
                break;
+       case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+               if (!intel_color_lut_entry_multi_equal(lut1, lut2,
+                                                      lut_size2, err))
+                       return false;
+               break;
        default:
                MISSING_CASE(gamma_mode);
                        return false;
@@ -1776,6 +1817,60 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
                crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
 
+static struct drm_property_blob *
+icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+       enum pipe pipe = crtc->pipe;
+       struct drm_property_blob *blob;
+       struct drm_color_lut *blob_data;
+       u32 i, val1, val2;
+
+       blob = drm_property_create_blob(&dev_priv->drm,
+                                       sizeof(struct drm_color_lut) * lut_size,
+                                       NULL);
+       if (IS_ERR(blob))
+               return NULL;
+
+       blob_data = blob->data;
+
+       I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+       for (i = 0; i < 9; i++) {
+               val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+               val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+
+               blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+                                  REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+               blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+                                    REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+               blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+                                   REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+       }
+
+       /*
+        * FIXME readouts from PAL_PREC_DATA register aren't giving correct values
+        * in the case of fine and coarse segments. Restricting readouts only for
+        * super fine segment as of now.
+        */
+
+       return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+       if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+           GAMMA_MODE_MODE_8BIT)
+               crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+       else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+                GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+               crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
+       else
+               crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
 void intel_color_init(struct intel_crtc *crtc)
 {
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1819,6 +1914,7 @@ void intel_color_init(struct intel_crtc *crtc)
 
                if (INTEL_GEN(dev_priv) >= 11) {
                        dev_priv->display.load_luts = icl_load_luts;
+                       dev_priv->display.read_luts = icl_read_luts;
                } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
                        dev_priv->display.load_luts = glk_load_luts;
                        dev_priv->display.read_luts = glk_read_luts;

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c64768976ac6ddf08685a784c41597b0515318b..9eb71a547103abe23899312f1c5467b10633bd53 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10410,6 +10410,12 @@ enum skl_power_gate {
 
 #define _PAL_PREC_MULTI_SEG_DATA_A     0x4A40C
 #define _PAL_PREC_MULTI_SEG_DATA_B     0x4AC0C
+#define  PAL_PREC_MULTI_SEG_RED_LDW_MASK   REG_GENMASK(29, 24)
+#define  PAL_PREC_MULTI_SEG_RED_UDW_MASK   REG_GENMASK(29, 20)
+#define  PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define  PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define  PAL_PREC_MULTI_SEG_BLUE_LDW_MASK  REG_GENMASK(9, 4)
+#define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
 
 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
                                        _PAL_PREC_MULTI_SEG_INDEX_A, \