ARM: dts: Add HSUSB2 EHCI Support to Logic PD DM37xx SOM-LV

The Logic PD SOM-LV has a USB Host Controller connected to 3-port
hub.  This enables the pin muxing for the host controller and
ehci-phy.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi
index aa9572bd930a8d41b3242affb8b6ce4774573958..365f39ff58bb8a512debeaa1645fc1feb980f75b 100644 (file)
--- a/arch/arm/boot/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi
@@ -23,6 +23,12 @@ wl12xx_vmmc: wl12xx_vmmc {
                enable-active-high;
                vin-supply = <&vmmc2>;
        };
+
+       /* HS USB Host PHY on PORT 1 */
+       hsusb2_phy: hsusb2_phy {
+               compatible = "usb-nop-xceiv";
+               reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
+       };
 };
 
 &gpmc {
@@ -126,7 +132,19 @@ wlcore: wlcore@2 {
        };
 };
 
+&usbhshost {
+       port2-mode = "ehci-phy";
+};
+
+&usbhsehci {
+       phys = <0 &hsusb2_phy>;
+};
+
+
 &omap3_pmx_core {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hsusb2_pins>;
+
        mmc3_pins: pinmux_mm3_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
@@ -164,6 +182,18 @@ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_so
                        OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
                >;
        };
+
+       hsusb2_pins: pinmux_hsusb2_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi1_cs3.hsusb2_data2 */
+                       OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_clk.hsusb2_data7 */
+                       OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_simo.hsusb2_data4 */
+                       OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_somi.hsusb2_data5 */
+                       OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs0.hsusb2_data6 */
+                       OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)       /* mcspi2_cs1.hsusb2_data3 */
+               >;
+       };
+
        hsusb_otg_pins: pinmux_hsusb_otg_pins {
                pinctrl-single,pins = <
                        OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
@@ -180,6 +210,33 @@ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)   /* hsusb0_data6.hsusb0_data6 */
                        OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
                >;
        };
+
+
+};
+
+&omap3_pmx_wkup {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hsusb2_reset_pin>;
+       hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
+               pinctrl-single,pins = <
+                       OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4)        /* sys_boot2.gpio_4 */
+               >;
+       };
+};
+
+&omap3_pmx_core2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&hsusb2_2_pins>;
+       hsusb2_2_pins: pinmux_hsusb2_2_pins {
+               pinctrl-single,pins = <
+                       OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)            /* etk_d10.hsusb2_clk */
+                       OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)            /* etk_d11.hsusb2_stp */
+                       OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d12.hsusb2_dir */
+                       OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d13.hsusb2_nxt */
+                       OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d14.hsusb2_data0 */
+                       OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)    /* etk_d15.hsusb2_data1 */
+               >;
+       };
 };
 
 &uart2 {