Merge tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre...

Pull "Fourth batch of cleanup for 4.1" from Nicolas Ferre:

- 1 issues revealed by the kbuild test robot fixed
- move of some functions and macros into relevant files to be able to
  streamline the at91 specific header afterwards

* tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
  ARM: at91/pm: move AT91_MEMCTRL_* to pm.h
  ARM: at91/pm: move the standby functions to pm.c
  ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected

diff --combined arch/arm/mach-at91/Makefile
index 06a4cefd33a07bf876e528d45077919404760faf,12440ec60924612cf612f5cae7b111d43f9c9f61..4fa8b4541e64fa06836c29863a574233a97227c8
--- 1/arch/arm/mach-at91/Makefile
--- 2/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@@ -1,15 -1,13 +1,15 @@@
  #
  # Makefile for the linux kernel.
  #
 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 +asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
  
  obj-y         := soc.o
  
  obj-$(CONFIG_SOC_AT91SAM9)    += sam9_smc.o
  
  # CPU-specific support
 -obj-$(CONFIG_SOC_AT91RM9200)  += at91rm9200.o at91rm9200_time.o
 +obj-$(CONFIG_SOC_AT91RM9200)  += at91rm9200.o
  obj-$(CONFIG_SOC_AT91SAM9)    += at91sam9.o
  obj-$(CONFIG_SOC_SAMA5)               += sama5.o
  
@@@ -17,6 -15,9 +17,9 @@@
  obj-$(CONFIG_PM)              += pm.o
  obj-$(CONFIG_PM)              += pm_suspend.o
  
+ ifeq ($(CONFIG_CPU_V7),y)
+ AFLAGS_pm_suspend.o := -march=armv7-a
+ endif
  ifeq ($(CONFIG_PM_DEBUG),y)
  CFLAGS_pm.o += -DDEBUG
  endif

diff --combined arch/arm/mach-at91/pm.c
index f93a735ba327dd862a1a1751f971900d4595d828,0a71c69618f8910c3f164bd2ac7675ec0a7bfe31..5062699cbb1258697c8f95046f30a125e4e14cae
--- 1/arch/arm/mach-at91/pm.c
--- 2/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@@ -32,18 -32,12 +32,18 @@@
  #include <asm/fncpy.h>
  #include <asm/cacheflush.h>
  
 -#include <mach/cpu.h>
 -#include <mach/hardware.h>
 -
  #include "generic.h"
  #include "pm.h"
  
 +/*
 + * FIXME: this is needed to communicate between the pinctrl driver and
 + * the PM implementation in the machine. Possibly part of the PM
 + * implementation should be moved down into the pinctrl driver and get
 + * called as part of the generic suspend/resume path.
 + */
 +extern void at91_pinctrl_gpio_suspend(void);
 +extern void at91_pinctrl_gpio_resume(void);
 +
  static struct {
        unsigned long uhp_udp_mask;
        int memctrl;
@@@ -222,6 -216,95 +222,95 @@@ static void at91_pm_set_standby(void (*
                at91_cpuidle_device.dev.platform_data = at91_standby;
  }
  
+ /*
+  * The AT91RM9200 goes into self-refresh mode with this command, and will
+  * terminate self-refresh automatically on the next SDRAM access.
+  *
+  * Self-refresh mode is exited as soon as a memory access is made, but we don't
+  * know for sure when that happens. However, we need to restore the low-power
+  * mode if it was enabled before going idle. Restoring low-power mode while
+  * still in self-refresh is "not recommended", but seems to work.
+  */
+ static void at91rm9200_standby(void)
+ {
+       u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
+ 
+       asm volatile(
+               "b    1f\n\t"
+               ".align    5\n\t"
+               "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
+               "    str    %0, [%1, %2]\n\t"
+               "    str    %3, [%1, %4]\n\t"
+               "    mcr    p15, 0, %0, c7, c0, 4\n\t"
+               "    str    %5, [%1, %2]"
+               :
+               : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
+                 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
+                 "r" (lpr));
+ }
+ 
+ /* We manage both DDRAM/SDRAM controllers, we need more than one value to
+  * remember.
+  */
+ static void at91_ddr_standby(void)
+ {
+       /* Those two values allow us to delay self-refresh activation
+        * to the maximum. */
+       u32 lpr0, lpr1 = 0;
+       u32 saved_lpr0, saved_lpr1 = 0;
+ 
+       if (at91_ramc_base[1]) {
+               saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+               lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+               lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+       }
+ 
+       saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+       lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
+       lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+ 
+       /* self-refresh mode now */
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
+       if (at91_ramc_base[1])
+               at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+ 
+       cpu_do_idle();
+ 
+       at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
+       if (at91_ramc_base[1])
+               at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
+ }
+ 
+ /* We manage both DDRAM/SDRAM controllers, we need more than one value to
+  * remember.
+  */
+ static void at91sam9_sdram_standby(void)
+ {
+       u32 lpr0, lpr1 = 0;
+       u32 saved_lpr0, saved_lpr1 = 0;
+ 
+       if (at91_ramc_base[1]) {
+               saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
+               lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
+               lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+       }
+ 
+       saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
+       lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
+       lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+ 
+       /* self-refresh mode now */
+       at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
+       if (at91_ramc_base[1])
+               at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+ 
+       cpu_do_idle();
+ 
+       at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
+       if (at91_ramc_base[1])
+               at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
+ }
+ 
  static const struct of_device_id ramc_ids[] __initconst = {
        { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
        { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },