Merge branch 'fixes-for-arm-soc' of git://sources.calxeda.com/kernel/linux into fixes

* 'fixes-for-arm-soc' of git://sources.calxeda.com/kernel/linux:
  ARM: make BSYM macro assembly only
  ARM: highbank: remove incorrect BSYM usage
  ARM: imx: remove incorrect BSYM usage
  ARM: exynos: remove incorrect BSYM usage
  ARM: ux500: add missing ENDPROC to headsmp.S
  ARM: msm: Add missing ENDPROC to headsmp.S
  ARM: versatile: Add missing ENDPROC to headsmp.S

diff --combined arch/arm/mach-exynos/platsmp.c
index 60bc45e3e7099045560f71bf4aaf29664341e488,b89bfa5b6b719a2030a9980669f6048bc60821b3..683aec786b78975bd8a791923134b1e0958de215
--- 1/arch/arm/mach-exynos/platsmp.c
--- 2/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@@ -24,7 -24,6 +24,6 @@@
  #include <asm/cacheflush.h>
  #include <asm/hardware/gic.h>
  #include <asm/smp_scu.h>
- #include <asm/unified.h>
  
  #include <mach/hardware.h>
  #include <mach/regs-clock.h>
@@@ -32,6 -31,7 +31,6 @@@
  
  #include <plat/cpu.h>
  
 -extern unsigned int gic_bank_offset;
  extern void exynos4_secondary_startup(void);
  
  #define CPU1_BOOT_REG         (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@@ -64,6 -64,31 +63,6 @@@ static void __iomem *scu_base_addr(void
  
  static DEFINE_SPINLOCK(boot_lock);
  
 -static void __cpuinit exynos4_gic_secondary_init(void)
 -{
 -      void __iomem *dist_base = S5P_VA_GIC_DIST +
 -                              (gic_bank_offset * smp_processor_id());
 -      void __iomem *cpu_base = S5P_VA_GIC_CPU +
 -                              (gic_bank_offset * smp_processor_id());
 -      int i;
 -
 -      /*
 -       * Deal with the banked PPI and SGI interrupts - disable all
 -       * PPI interrupts, ensure all SGI interrupts are enabled.
 -       */
 -      __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
 -      __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
 -
 -      /*
 -       * Set priority on PPI and SGI interrupts
 -       */
 -      for (i = 0; i < 32; i += 4)
 -              __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
 -
 -      __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
 -      __raw_writel(1, cpu_base + GIC_CPU_CTRL);
 -}
 -
  void __cpuinit platform_secondary_init(unsigned int cpu)
  {
        /*
@@@ -71,7 -96,7 +70,7 @@@
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
 -      exynos4_gic_secondary_init();
 +      gic_secondary_init(0);
  
        /*
         * let the primary processor know we're out of the
@@@ -137,7 -162,7 +136,7 @@@ int __cpuinit boot_secondary(unsigned i
        while (time_before(jiffies, timeout)) {
                smp_rmb();
  
-               __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+               __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
                gic_raise_softirq(cpumask_of(cpu), 1);
  
@@@ -192,6 -217,6 +191,6 @@@ void __init platform_smp_prepare_cpus(u
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-       __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+       __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
  }

diff --combined arch/arm/mach-highbank/highbank.c
index 804c4a55f8038c75cbf0731168ee6d0d36de004a,48293f8b4bd34773dfc01685dbad19fa76febfb3..7afbe1e55bebe710f926b01dbb84846de4ca0e9d
--- 1/arch/arm/mach-highbank/highbank.c
--- 2/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@@ -25,7 -25,6 +25,6 @@@
  #include <linux/smp.h>
  
  #include <asm/cacheflush.h>
- #include <asm/unified.h>
  #include <asm/smp_scu.h>
  #include <asm/hardware/arm_timer.h>
  #include <asm/hardware/timer-sp.h>
@@@ -76,7 -75,7 +75,7 @@@ void highbank_set_cpu_jump(int cpu, voi
  #ifdef CONFIG_SMP
        cpu = cpu_logical_map(cpu);
  #endif
-       writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+       writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
                          HB_JUMP_TABLE_PHYS(cpu) + 15);
@@@ -144,8 -143,6 +143,8 @@@ DT_MACHINE_START(HIGHBANK, "Highbank"
        .map_io         = highbank_map_io,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
 +      .handle_irq     = gic_handle_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
 +      .restart        = highbank_restart,
  MACHINE_END

diff --combined arch/arm/mach-imx/src.c
index 4bde04f99e38ceda85fd4cb43f89bf2eb080ead7,74a4b5d3d1c0e91939803cd6b712ba5c2aed116f..29bd1243781ede5156ca622de5fccbba82160947
--- 1/arch/arm/mach-imx/src.c
--- 2/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@@ -15,11 -15,9 +15,10 @@@
  #include <linux/of.h>
  #include <linux/of_address.h>
  #include <linux/smp.h>
- #include <asm/unified.h>
  
  #define SRC_SCR                               0x000
  #define SRC_GPR1                      0x020
 +#define BP_SRC_SCR_WARM_RESET_ENABLE  0
  #define BP_SRC_SCR_CORE1_RST          14
  #define BP_SRC_SCR_CORE1_ENABLE               22
  
@@@ -43,37 -41,15 +42,37 @@@ void imx_enable_cpu(int cpu, bool enabl
  void imx_set_cpu_jump(int cpu, void *jump_addr)
  {
        cpu = cpu_logical_map(cpu);
-       writel_relaxed(BSYM(virt_to_phys(jump_addr)),
+       writel_relaxed(virt_to_phys(jump_addr),
                       src_base + SRC_GPR1 + cpu * 8);
  }
  
 +void imx_src_prepare_restart(void)
 +{
 +      u32 val;
 +
 +      /* clear enable bits of secondary cores */
 +      val = readl_relaxed(src_base + SRC_SCR);
 +      val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
 +      writel_relaxed(val, src_base + SRC_SCR);
 +
 +      /* clear persistent entry register of primary core */
 +      writel_relaxed(0, src_base + SRC_GPR1);
 +}
 +
  void __init imx_src_init(void)
  {
        struct device_node *np;
 +      u32 val;
  
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
        src_base = of_iomap(np, 0);
        WARN_ON(!src_base);
 +
 +      /*
 +       * force warm reset sources to generate cold reset
 +       * for a more reliable restart
 +       */
 +      val = readl_relaxed(src_base + SRC_SCR);
 +      val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
 +      writel_relaxed(val, src_base + SRC_SCR);
  }