clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845

QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Use new macro, split out init structures so they
don't have to be copied]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index fa1a196350f1542ab5acf95528b7b329ecaddb98..42ab01d33b525e35df29a47bbe099f1601f1f7fa 100644 (file)
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -396,18 +396,27 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        { }
 };
 
+static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
+       .name = "gcc_qupv3_wrap0_s0_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
+};
+
 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
        .cmd_rcgr = 0x17034,
        .mnd_width = 16,
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s0_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
+       .name = "gcc_qupv3_wrap0_s1_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -416,12 +425,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s1_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
+       .name = "gcc_qupv3_wrap0_s2_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -430,12 +441,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s2_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
+       .name = "gcc_qupv3_wrap0_s3_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -444,12 +457,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s3_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
+       .name = "gcc_qupv3_wrap0_s4_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -458,12 +473,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s4_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
+       .name = "gcc_qupv3_wrap0_s5_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -472,12 +489,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s5_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
+       .name = "gcc_qupv3_wrap0_s6_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -486,12 +505,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s6_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
+       .name = "gcc_qupv3_wrap0_s7_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -500,12 +521,14 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap0_s7_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
+       .name = "gcc_qupv3_wrap1_s0_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -514,12 +537,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s0_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
+       .name = "gcc_qupv3_wrap1_s1_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -528,12 +553,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s1_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
+       .name = "gcc_qupv3_wrap1_s2_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -542,12 +569,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s2_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
+       .name = "gcc_qupv3_wrap1_s3_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -556,12 +585,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s3_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
+       .name = "gcc_qupv3_wrap1_s4_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -570,12 +601,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s4_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
+       .name = "gcc_qupv3_wrap1_s5_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -584,12 +617,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s5_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
+       .name = "gcc_qupv3_wrap1_s6_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -598,12 +633,14 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s6_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
+};
+
+static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
+       .name = "gcc_qupv3_wrap1_s7_clk_src",
+       .parent_names = gcc_parent_names_0,
+       .num_parents = 4,
+       .ops = &clk_rcg2_shared_ops,
 };
 
 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -612,12 +649,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
        .hid_width = 5,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
-       .clkr.hw.init = &(struct clk_init_data){
-               .name = "gcc_qupv3_wrap1_s7_clk_src",
-               .parent_names = gcc_parent_names_0,
-               .num_parents = 4,
-               .ops = &clk_rcg2_shared_ops,
-       },
+       .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
 };
 
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
@@ -3458,9 +3490,29 @@ static const struct of_device_id gcc_sdm845_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
 
+static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
+       DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
+};
+
 static int gcc_sdm845_probe(struct platform_device *pdev)
 {
        struct regmap *regmap;
+       int ret;
 
        regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
        if (IS_ERR(regmap))
@@ -3470,6 +3522,11 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
        regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
        regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
 
+       ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
+                                       ARRAY_SIZE(gcc_dfs_clocks));
+       if (ret)
+               return ret;
+
        return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
 }