]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
MIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms
authorJaedon Shin <jaedon.shin@gmail.com>
Fri, 8 May 2015 12:59:18 +0000 (21:59 +0900)
committerRalf Baechle <ralf@linux-mips.org>
Sun, 21 Jun 2015 19:53:35 +0000 (21:53 +0200)
Add two uart device nodes known as the uart1 and uart2 for the bcm7xxx
platforms.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9991/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/boot/dts/brcm/bcm7346.dtsi
arch/mips/boot/dts/brcm/bcm7358.dtsi
arch/mips/boot/dts/brcm/bcm7360.dtsi
arch/mips/boot/dts/brcm/bcm7362.dtsi
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
arch/mips/boot/dts/brcm/bcm97358svmb.dts
arch/mips/boot/dts/brcm/bcm97360svmb.dts
arch/mips/boot/dts/brcm/bcm97362svmb.dts

index 1f30728a317719968a9acf371b04f0e54087ae24..d817bb46b934fd1cb81388dd0d492f55c74171ed 100644 (file)
@@ -24,6 +24,8 @@ cpu@1 {
 
        aliases {
                uart0 = &uart0;
+               uart1 = &uart1;
+               uart2 = &uart2;
        };
 
        cpu_intc: cpu_intc {
@@ -118,6 +120,30 @@ uart0: serial@406900 {
                        status = "disabled";
                };
 
+               uart1: serial@406940 {
+                       compatible = "ns16550a";
+                       reg = <0x406940 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <65>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@406980 {
+                       compatible = "ns16550a";
+                       reg = <0x406980 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <66>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
                enet0: ethernet@430000 {
                        phy-mode = "internal";
                        phy-handle = <&phy1>;
index 2c2aa9368f76fb12a0ac77d6b52caff2fa96faa2..277a90adc1a78cb07834dd7c870ac374cc1557da 100644 (file)
@@ -18,6 +18,8 @@ cpu@0 {
 
        aliases {
                uart0 = &uart0;
+               uart1 = &uart1;
+               uart2 = &uart2;
        };
 
        cpu_intc: cpu_intc {
@@ -112,6 +114,30 @@ uart0: serial@406800 {
                        status = "disabled";
                };
 
+               uart1: serial@406840 {
+                       compatible = "ns16550a";
+                       reg = <0x406840 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <62>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@406880 {
+                       compatible = "ns16550a";
+                       reg = <0x406880 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <63>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
                enet0: ethernet@430000 {
                        phy-mode = "internal";
                        phy-handle = <&phy1>;
index f23b0aed276f96b7eb31fc9b1291ac0078f28f8b..9e1e571ba346ad7a240faf5a18a54b3f108e3cc7 100644 (file)
@@ -18,6 +18,8 @@ cpu@0 {
 
        aliases {
                uart0 = &uart0;
+               uart1 = &uart1;
+               uart2 = &uart2;
        };
 
        cpu_intc: cpu_intc {
@@ -112,6 +114,30 @@ uart0: serial@406800 {
                        status = "disabled";
                };
 
+               uart1: serial@406840 {
+                       compatible = "ns16550a";
+                       reg = <0x406840 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <62>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@406880 {
+                       compatible = "ns16550a";
+                       reg = <0x406880 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <63>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
                enet0: ethernet@430000 {
                        phy-mode = "internal";
                        phy-handle = <&phy1>;
index da99db665bbc66e7b75819e29904c4547f72e0ab..6e65db86fc618471df11f543b2569872d36f85b4 100644 (file)
@@ -24,6 +24,8 @@ cpu@1 {
 
        aliases {
                uart0 = &uart0;
+               uart1 = &uart1;
+               uart2 = &uart2;
        };
 
        cpu_intc: cpu_intc {
@@ -118,6 +120,30 @@ uart0: serial@406800 {
                        status = "disabled";
                };
 
+               uart1: serial@406840 {
+                       compatible = "ns16550a";
+                       reg = <0x406840 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <62>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
+               uart2: serial@406880 {
+                       compatible = "ns16550a";
+                       reg = <0x406880 0x20>;
+                       reg-io-width = <0x4>;
+                       reg-shift = <0x2>;
+                       native-endian;
+                       interrupt-parent = <&periph_intc>;
+                       interrupts = <63>;
+                       clocks = <&uart_clk>;
+                       status = "disabled";
+               };
+
                enet0: ethernet@430000 {
                        phy-mode = "internal";
                        phy-handle = <&phy1>;
index 70f196d89d26efb487db92b64ef9a8d21c523d22..3fe0445b9d37bae86ed53564b09747bd321653dd 100644 (file)
@@ -21,6 +21,14 @@ &uart0 {
        status = "okay";
 };
 
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
 &enet0 {
        status = "okay";
 };
index d18e6d9477398129263582042c42152798385e08..a8dc01e3031317f577db8e5c5bfc8f08363b045a 100644 (file)
@@ -21,6 +21,14 @@ &uart0 {
        status = "okay";
 };
 
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
 &enet0 {
        status = "okay";
 };
index 4fe51550010258777b1bfb3c892acf8aeb3f4ce8..eee8b0e32681541266b70caa5d4b07ff789d35aa 100644 (file)
@@ -21,6 +21,14 @@ &uart0 {
        status = "okay";
 };
 
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
 &enet0 {
        status = "okay";
 };
index b7b88e5dc9e7714c95f7c7caddafd67714297599..739c2ef5663b5cec059ee167cbb92451bc010db7 100644 (file)
@@ -21,6 +21,14 @@ &uart0 {
        status = "okay";
 };
 
+&uart1 {
+       status = "okay";
+};
+
+&uart2 {
+       status = "okay";
+};
+
 &enet0 {
        status = "okay";
 };