]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
s390: rename psw_bits enums
authorHeiko Carstens <heiko.carstens@de.ibm.com>
Sat, 3 Jun 2017 08:19:55 +0000 (10:19 +0200)
committerMartin Schwidefsky <schwidefsky@de.ibm.com>
Mon, 12 Jun 2017 14:26:02 +0000 (16:26 +0200)
The address space enums that must be used when modifying the address
space part of a psw with the psw_bits() macro can easily be confused
with the psw defines that are used to mask and compare directly the
mask part of a psw.
We have e.g. PSW_AS_PRIMARY vs PSW_ASC_PRIMARY.

To avoid confusion rename the PSW_AS_* enums to PSW_BITS_AS_*.

In addition also rename the PSW_AMODE_* enums, so they also follow the
same naming scheme: PSW_BITS_AMODE_*.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
arch/s390/include/asm/ptrace.h
arch/s390/kernel/uprobes.c
arch/s390/kvm/gaccess.c
arch/s390/kvm/gaccess.h
arch/s390/kvm/guestdbg.c
arch/s390/kvm/priv.c
arch/s390/mm/init.c

index 99bc456cc26a3087cbec7f35ca82959a94cf2ab3..c8d13bcc9f5d6d6114980d8757af50f619445e7a 100644 (file)
@@ -46,16 +46,16 @@ struct psw_bits {
 };
 
 enum {
-       PSW_AMODE_24BIT = 0,
-       PSW_AMODE_31BIT = 1,
-       PSW_AMODE_64BIT = 3
+       PSW_BITS_AMODE_24BIT = 0,
+       PSW_BITS_AMODE_31BIT = 1,
+       PSW_BITS_AMODE_64BIT = 3
 };
 
 enum {
-       PSW_AS_PRIMARY   = 0,
-       PSW_AS_ACCREG    = 1,
-       PSW_AS_SECONDARY = 2,
-       PSW_AS_HOME      = 3
+       PSW_BITS_AS_PRIMARY     = 0,
+       PSW_BITS_AS_ACCREG      = 1,
+       PSW_BITS_AS_SECONDARY   = 2,
+       PSW_BITS_AS_HOME        = 3
 };
 
 #define psw_bits(__psw) (*({                   \
index 314e0ee3016a343dd639bc9b2f8394879ed0ee41..0eec45b4575bf404f2cef4ad96262dc78a285941 100644 (file)
@@ -27,9 +27,9 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
 
 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
 {
-       if (psw_bits(regs->psw).eaba == PSW_AMODE_24BIT)
+       if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
                return -EINVAL;
-       if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_AMODE_31BIT)
+       if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
                return -EINVAL;
        clear_pt_regs_flag(regs, PIF_PER_TRAP);
        auprobe->saved_per = psw_bits(regs->psw).r;
@@ -372,8 +372,8 @@ static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs)
 
 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
 {
-       if ((psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) ||
-           ((psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) &&
+       if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||
+           ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
             !is_compat_task())) {
                regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
                do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);
index 9da243d94cc3286c5e1dabcfae5e563f991326a0..6ad4a9797de803bcfa3c3cf964b59c14cee02245 100644 (file)
@@ -557,20 +557,20 @@ static int get_vcpu_asce(struct kvm_vcpu *vcpu, union asce *asce,
                return 0;
        }
 
-       if (mode == GACC_IFETCH)
-               psw.as = psw.as == PSW_AS_HOME ? PSW_AS_HOME : PSW_AS_PRIMARY;
+       if ((mode == GACC_IFETCH) && (psw.as != PSW_BITS_AS_HOME))
+               psw.as = PSW_BITS_AS_PRIMARY;
 
        switch (psw.as) {
-       case PSW_AS_PRIMARY:
+       case PSW_BITS_AS_PRIMARY:
                asce->val = vcpu->arch.sie_block->gcr[1];
                return 0;
-       case PSW_AS_SECONDARY:
+       case PSW_BITS_AS_SECONDARY:
                asce->val = vcpu->arch.sie_block->gcr[7];
                return 0;
-       case PSW_AS_HOME:
+       case PSW_BITS_AS_HOME:
                asce->val = vcpu->arch.sie_block->gcr[13];
                return 0;
-       case PSW_AS_ACCREG:
+       case PSW_BITS_AS_ACCREG:
                rc = ar_translation(vcpu, asce, ar, mode);
                if (rc > 0)
                        return trans_exc(vcpu, rc, ga, ar, mode, PROT_TYPE_ALC);
index 7ce47fd36f2872b08078c07191711dc870aa62a6..bec42b852246f0c44f88acf20ae36c51a36c3d20 100644 (file)
@@ -57,9 +57,9 @@ static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu,
 {
        psw_t *psw = &vcpu->arch.sie_block->gpsw;
 
-       if (psw_bits(*psw).eaba == PSW_AMODE_64BIT)
+       if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)
                return ga;
-       if (psw_bits(*psw).eaba == PSW_AMODE_31BIT)
+       if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)
                return ga & ((1UL << 31) - 1);
        return ga & ((1UL << 24) - 1);
 }
index 23d9a4e12da1fe552b63d921f0fe23855f830d65..c2e0ddc1356e551ebd8c466b73956e2574b67436 100644 (file)
@@ -613,15 +613,15 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu)
                 * instruction. Check primary and home space-switch-event
                 * controls. (theoretically home -> home produced no event)
                 */
-               if (((new_as == PSW_AS_HOME) ^ old_as_is_home(vcpu)) &&
-                    (pssec(vcpu) || hssec(vcpu)))
+               if (((new_as == PSW_BITS_AS_HOME) ^ old_as_is_home(vcpu)) &&
+                   (pssec(vcpu) || hssec(vcpu)))
                        vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
 
                /*
                 * PT, PTI, PR, PC instruction operate on primary AS only. Check
                 * if the primary-space-switch-event control was or got set.
                 */
-               if (new_as == PSW_AS_PRIMARY && !old_as_is_home(vcpu) &&
+               if (new_as == PSW_BITS_AS_PRIMARY && !old_as_is_home(vcpu) &&
                    (pssec(vcpu) || old_ssec(vcpu)))
                        vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
        }
index c03106c428cfa89e1f25297efbd2d667a73b5fd7..e9dd7efc57b8f5088c098175c679737bf48b7796 100644 (file)
@@ -361,7 +361,7 @@ static int handle_sske(struct kvm_vcpu *vcpu)
                }
        }
        if (m3 & SSKE_MB) {
-               if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT)
+               if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT)
                        vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK;
                else
                        vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL;
@@ -901,7 +901,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
                /* only support 2G frame size if EDAT2 is available and we are
                   not in 24-bit addressing mode */
                if (!test_kvm_facility(vcpu->kvm, 78) ||
-                   psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_24BIT)
+                   psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_24BIT)
                        return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
                end = (start + (1UL << 31)) & ~((1UL << 31) - 1);
                break;
@@ -938,7 +938,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
                start += PAGE_SIZE;
        }
        if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) {
-               if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT) {
+               if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT) {
                        vcpu->run->s.regs.gprs[reg2] = end;
                } else {
                        vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL;
index 0352f9f88c73275c69b416e5bbf1597732899f3d..bc8c301f82b6289f0c5910f8e6fc9b4460bd1252 100644 (file)
@@ -103,7 +103,7 @@ void __init paging_init(void)
        __ctl_load(S390_lowcore.kernel_asce, 13, 13);
        psw.mask = __extract_psw();
        psw_bits(psw).t = 1;
-       psw_bits(psw).as = PSW_AS_HOME;
+       psw_bits(psw).as = PSW_BITS_AS_HOME;
        __load_psw_mask(psw.mask);
 
        sparse_memory_present_with_active_regions(MAX_NUMNODES);