arm64: tegra: Add XUSB and pad controller on Tegra186

Adds the XUSB pad and XUSB controllers on Tegra186.

Reviewed-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 6e2b6ce99df2074ead427b3e9c30d60a7446eb1d..f0bb6ced49765761293d185e80238a794f18cbb8 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -341,6 +341,141 @@ hda@3510000 {
                status = "disabled";
        };
 
+       padctl: padctl@3520000 {
+               compatible = "nvidia,tegra186-xusb-padctl";
+               reg = <0x0 0x03520000 0x0 0x1000>,
+                     <0x0 0x03540000 0x0 0x1000>;
+               reg-names = "padctl", "ao";
+
+               resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
+               reset-names = "padctl";
+
+               status = "disabled";
+
+               pads {
+                       usb2 {
+                               clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
+                               clock-names = "trk";
+                               status = "disabled";
+
+                               lanes {
+                                       usb2-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb2-1 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb2-2 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+
+                       hsic {
+                               clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
+                               clock-names = "trk";
+                               status = "disabled";
+
+                               lanes {
+                                       hsic-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+
+                       usb3 {
+                               status = "disabled";
+
+                               lanes {
+                                       usb3-0 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb3-1 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+
+                                       usb3-2 {
+                                               status = "disabled";
+                                               #phy-cells = <0>;
+                                       };
+                               };
+                       };
+               };
+
+               ports {
+                       usb2-0 {
+                               status = "disabled";
+                       };
+
+                       usb2-1 {
+                               status = "disabled";
+                       };
+
+                       usb2-2 {
+                               status = "disabled";
+                       };
+
+                       hsic-0 {
+                               status = "disabled";
+                       };
+
+                       usb3-0 {
+                               status = "disabled";
+                       };
+
+                       usb3-1 {
+                               status = "disabled";
+                       };
+
+                       usb3-2 {
+                               status = "disabled";
+                       };
+               };
+       };
+
+       usb@3530000 {
+               compatible = "nvidia,tegra186-xusb";
+               reg = <0x0 0x03530000 0x0 0x8000>,
+                     <0x0 0x03538000 0x0 0x1000>;
+               reg-names = "hcd", "fpci";
+
+               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+
+               clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
+                        <&bpmp TEGRA186_CLK_XUSB_FALCON>,
+                        <&bpmp TEGRA186_CLK_XUSB_SS>,
+                        <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
+                        <&bpmp TEGRA186_CLK_CLK_M>,
+                        <&bpmp TEGRA186_CLK_XUSB_FS>,
+                        <&bpmp TEGRA186_CLK_PLLU>,
+                        <&bpmp TEGRA186_CLK_CLK_M>,
+                        <&bpmp TEGRA186_CLK_PLLE>;
+               clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
+                             "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
+                             "pll_u_480m", "clk_m", "pll_e";
+
+               power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
+                               <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
+               power-domain-names = "xusb_host", "xusb_ss";
+               nvidia,xusb-padctl = <&padctl>;
+
+               status = "disabled";
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
        fuse@3820000 {
                compatible = "nvidia,tegra186-efuse";
                reg = <0x0 0x03820000 0x0 0x10000>;