]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
Revert "drm/amdgpu: remove fence fallback"
authorAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Fri, 21 Sep 2018 18:48:50 +0000 (14:48 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Sep 2018 02:09:13 +0000 (21:09 -0500)
This reverts commit 9b0df0937a852d299fbe42a5939c9a8a4cc83c55.
This commit breaks KCQ IB test and S3 on Polaris 11.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

index 6cb35e3dab30e4806b8057822d459cbaf82effb3..c43bc83c2d29af6a20bf7d4e3e9fd214623883bb 100644 (file)
@@ -146,6 +146,7 @@ extern int amdgpu_cik_support;
 #define AMDGPU_DEFAULT_GTT_SIZE_MB             3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS         3000
 #define AMDGPU_MAX_USEC_TIMEOUT                        100000  /* 100 ms */
+#define AMDGPU_FENCE_JIFFIES_TIMEOUT           (HZ / 2)
 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
 #define AMDGPU_IB_POOL_SIZE                    16
 #define AMDGPU_DEBUGFS_MAX_COMPONENTS          32
index 176f28777f5e558254c211ab3f7797c9fc34a019..da36731460b56c93e16f12461b80f6fb7b589e88 100644 (file)
@@ -195,6 +195,19 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
        return 0;
 }
 
+/**
+ * amdgpu_fence_schedule_fallback - schedule fallback check
+ *
+ * @ring: pointer to struct amdgpu_ring
+ *
+ * Start a timer as fallback to our interrupts.
+ */
+static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
+{
+       mod_timer(&ring->fence_drv.fallback_timer,
+                 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
+}
+
 /**
  * amdgpu_fence_process - check for fence activity
  *
@@ -216,6 +229,9 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
 
        } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 
+       if (seq != ring->fence_drv.sync_seq)
+               amdgpu_fence_schedule_fallback(ring);
+
        if (unlikely(seq == last_seq))
                return;
 
@@ -246,6 +262,21 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
        } while (last_seq != seq);
 }
 
+/**
+ * amdgpu_fence_fallback - fallback for hardware interrupts
+ *
+ * @work: delayed work item
+ *
+ * Checks for fence activity.
+ */
+static void amdgpu_fence_fallback(struct timer_list *t)
+{
+       struct amdgpu_ring *ring = from_timer(ring, t,
+                                             fence_drv.fallback_timer);
+
+       amdgpu_fence_process(ring);
+}
+
 /**
  * amdgpu_fence_wait_empty - wait for all fences to signal
  *
@@ -393,6 +424,8 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
        atomic_set(&ring->fence_drv.last_seq, 0);
        ring->fence_drv.initialized = false;
 
+       timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
+
        ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
        spin_lock_init(&ring->fence_drv.lock);
        ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
@@ -468,6 +501,7 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
                amdgpu_irq_put(adev, ring->fence_drv.irq_src,
                               ring->fence_drv.irq_type);
                drm_sched_fini(&ring->sched);
+               del_timer_sync(&ring->fence_drv.fallback_timer);
                for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
                        dma_fence_put(ring->fence_drv.fences[j]);
                kfree(ring->fence_drv.fences);
@@ -560,6 +594,27 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
        return (const char *)fence->ring->name;
 }
 
+/**
+ * amdgpu_fence_enable_signaling - enable signalling on fence
+ * @fence: fence
+ *
+ * This function is called with fence_queue lock held, and adds a callback
+ * to fence_queue that checks if this fence is signaled, and if so it
+ * signals the fence and removes itself.
+ */
+static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
+{
+       struct amdgpu_fence *fence = to_amdgpu_fence(f);
+       struct amdgpu_ring *ring = fence->ring;
+
+       if (!timer_pending(&ring->fence_drv.fallback_timer))
+               amdgpu_fence_schedule_fallback(ring);
+
+       DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
+
+       return true;
+}
+
 /**
  * amdgpu_fence_free - free up the fence memory
  *
@@ -590,6 +645,7 @@ static void amdgpu_fence_release(struct dma_fence *f)
 static const struct dma_fence_ops amdgpu_fence_ops = {
        .get_driver_name = amdgpu_fence_get_driver_name,
        .get_timeline_name = amdgpu_fence_get_timeline_name,
+       .enable_signaling = amdgpu_fence_enable_signaling,
        .release = amdgpu_fence_release,
 };
 
index 44fc665e45771346705a623b57b9bf66f96fdd8d..9cc239968e4062f58fdbe85446600cb7dd8f82ba 100644 (file)
@@ -77,6 +77,7 @@ struct amdgpu_fence_driver {
        bool                            initialized;
        struct amdgpu_irq_src           *irq_src;
        unsigned                        irq_type;
+       struct timer_list               fallback_timer;
        unsigned                        num_fences_mask;
        spinlock_t                      lock;
        struct dma_fence                **fences;