To avoid people reading this code being very confused, add a comment
clarifying the need for invert resets on some chip revisions.
Suggested-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
u32 slot = port->slot;
u32 val = 0;
+ /*
+ * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at
+ * the end of the chip_id has inverted PCI resets.
+ */
mt7621_reset_port(port);
val = read_config(pcie, slot, PCIE_FTS_NUM);